MSI
(Cache Coherence Protocol)
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In a multiprocessor system, MSI ( Modified -Shared-Invalid ) is the most basic cache coherence protocol. Each block ( block ) in the cache includes 3 states: Modified ( M , modified), Shared (S , shared ) , Invalid ( I , invalid ) .
Modified
Indicates that the block ( block ) in the cache has been modified. At this time, the data in the cache is inconsistent with the back-end storage (eg, memory). When the cache is evicted (memory is evicted, the block " block " data will be lost), the cache is responsible for writing the " M " state ( Modified ) block ( block ) back to the backend storage.
Shared
Indicates that the block ( block ) in the cache has not been modified, and there is a read-only state in at least one cache (block " block " data in the cache is read and copied). Block ( block ) data in the cache can be evicted ( memory is evicted, block " block " data will be lost ) without writing back to backend storage.
Invalid
Indicates that the block ( block ) does not exist in the current cache. At this time, if the block ( block ) needs to be stored in this cache, it must be read from memory or other caches.
These coherent states are maintained by maintaining communication between the cache and the backend storage. A cache plays a different role when reading a block or writing a block , or reading or writing a block from another cache .
On a cache, if a request is made to read a block in the " M " or " S " state , the cache serves the data directly. If the read block is not in the cache (in the " I " state), the cache must check that the block with the " M " state (copy) does not exist in other caches . Different cache architectures have different handling. For example, the bus architecture, if the read request is broadcast to all caches, this architecture generally knows which caches have a copy of the cache block ( block ) recently by means of snooping . Other architectures include the cache directory, which uses a proxy directory (a proxy, but also a directory) to know which caches have a copy of the cache block ( block ) recently. If there is a block (copy) with " M " state in other caches , the mixed memory must write this block ( block , copy) data back to the backend storage and set the block ( block ) to " S " or " I " state . Once the block (copy) data of all other caches in " M " state are all written back to the backend storage, the cache can read from the backend storage, or read the corresponding " S " state block from other caches ( block , copy). This way, the cache can serve the data (for read requests). After that, the cached block ( block) is set to the " S " state.
如果请求写入一个“M”状态的块（block），缓存直接修改本地数据。如果写入的块（block）处于“S”状态，缓存必须通知其他所有存在“S”状态的块（拷贝）的缓存，其他缓存必须收回（内存被收回，块“block”数据将丢失）对应的块（拷贝）。这个通知可以通过如上总线侦听窥探的方式（总线架构），或者通过代理目录（一种代理，也是一种目录）的方式（缓存目录架构）。之后才能修改本地数据。如果写入的块（block）处于“I”状态，缓存必须通知其他所有存在“S”或者“M”状态的块（拷贝）的缓存，其他缓存必须收回（内存被收回，块“block”数据将丢失）对应的块（block，拷贝）。如果对应的块（拷贝）处于“M”状态，缓存必须将对应的块（block，拷贝）写回后端存储，或者将对应的块（block，拷贝）提供给请求的缓存。如果这个时候正好在本地还没有写入的块，在修改之前，将先从后端存储中读进来。块（block）修改之后，设置缓存块为“M”状态。
对于任何两个给定的缓存，某个块（block，包括拷贝）允许的状态如下：
M S I
M n n y
S n y y
I y y y
<!--[if !supportLists]-->1、 <!--[endif]-->https://en.wikipedia.org/wiki/MSI_protocol
<!--[if !supportLists]-->2、 <!--[endif]-->https://en.wikipedia.org/wiki/Cache_coherence
<!--[if !supportLists]-->3、 <!--[endif]-->Cache Coherence，https://www.cs.auckland.ac.nz/~jmor159/363/html/cache_coh.html
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