1, the concept of sequential statements
Features sequential statements are executed sequentially every order of the statements is consistent with their written order. Sequential statements can only appear in the process (process) and subroutines,
Including function subroutine (function) and the process (procedure).
2. species
Process statements, assignment statements, flow control statements, wait statement, subroutine call statement, return statement, no operation statement.
a. Statement process (process statement)
Statement is a process sequential statements constituted by the rest of the structure of the exchange of information with the signal, a signal list in the process sensitive, any signal changes listed in the table will start the process,
Implementation of the corresponding sequential statements inside the process. The parallel process statement is one of the hallmarks separate statements and sequential statements area.
[Process label:] process [(sensitive signal list)] [(variable declarations)]% variable declaration
begin
Sequential statements;
end process；
b. Assignment statements
Assignment statements include variable assignments and signal assignment statements, the former assignment is happening at once, the latter assignment occurs at a time at which a process, and delays were.
Variable assignment target: = source assignment
Signal assignment target <= assignment source
In the same process, the same signal assignment target when there are multiple assignments source, signal assignment is the final goal of obtaining a source of value assignment, which is the same goal in front of the assignment without any changes.
signal s1,s2:std_logic;
signal sec:std_logic_vector(0 to 7);
process(s1,s2)
variable v1,v2:std_logic;
begin
v1 = '1';
v2:='1';
s1<='1';
s2<='1';
sec(0)<=v1;
sec(1)<=v2;
sec(2)<=s1;
sec(3)<=s2;
v1 = '0';
v2:='0';
s2<='0';
sec(4)<=v1;
sec(5)<=v2;
sec(6)<=s1;
sec(7)<=s2;
end process;
sec="01000111"
c. signal and variable assignments
Target identifier assignment
variable a,b:std_logic;
sigal c:std_logic_vector(1 to 4);
a:='1';
b:='0';
c<="1100";
c(3)<='1';
Note: a value in single quotes, double quotes a number of value
2. Paragraph assignment
signal c:std_logic_vector(1 to 4);
c(1 to 2)<='10';
c(1 to 4)<="1010";
3. Block Assignment