table of Contents
VHDL operator error prone
1, "&" and "and"
. (1) & means is connected, such as two bit signals a, b through c <= "a & b" to synthesize a 2-bit signal C;
(2). and logic means "and";
2 "/ ="
indicates not equal to
3. in addition there is a shift, like the exclusive oR operator, to the look-up table to time;
4. Note also that the operator priority;
VHDL statement
1.VHDL parallel statement
Parallel signal assignment statement
Overview: assignment target may be variable or signal. In parallel statement, usually only to the assignment signal;
1. Simple signal assignment statement
format: evaluation target signal <= Expression
2. Conditions signal assignment statement
format: evaluation target signal <= assignment condition expression when the else
{expression when else} assignment condition
expressions;
wherein: when after the first when condition is not satisfied, it is determined to continue a condition;
3. selection signal assignment statement
with an expression select choice
evaluation target signal <= expression when selecting values,
{expression when formula selected value}
expression when selection value;
wherein, when the selected value of the expression is changed, it starts the corresponding sentence;
Note: conditions after when often wrong, as if the definition of a variable of four , the condition is written as when "0001", ( be sure to use double quotes ), if a variable , use single quotes .
Process statement
1. The format
process (Table sensitive signals)
the begin
sequence described statements;
End Process;
2. Note: the sensitivity signal table is "signal" list, changes in the signal table will cause implementation process, all the changes and processes performed initiator signal should be included in the table;
Block statement
Follow-up on
Component instantiation statement
