The basic structure of the program VHDL

(1) LIBRARY statement and PACHAGE part

      Action: library (Library) is used to store pre-compiled programs (Package), defines a data package assembly, logical operations and components. Mainly in the constant declarations, data types, elements and subsystems in the physical design or the like is used.

     Use Format: LIBRARY library name;

         . USE library name package name .ALL;

For example: LIBRARY IEEE;

               USE IEEE.STD_LOGIC_1164.ALL;

     (2) ENTITY defined

      Action: the definition of the design input / output ports, i.e. the appearance of the circuit, i.e., I / O type and number of interfaces using the format:

     format:

              ENTITY entity name of the IS

             Port (Port: port mode data type;

       ........

                    Port Name: Port mode data types;

    )

    END entity name;

Example:     

ENTITY MUX41A IS
PORT (A,B,C,D,s0,s1,s2,s3 :IN STD_LOGIC;
Y : OUT STD_LOGIC);
END ENTITY MUX41A;

(3) ARCHITECTURE defined

    Role: implementation-defined entity. That is specifically described circuit, a circuit or what action to realize the function.

Using the format:

 ARCHITECTURE structure name of the entity name IS

begin       

     Description Statement;

end structure name;

E.g:

ARCHITECTURE BHV OF MUX41A IS
SIGNAL S:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
S <= s3 & s2 & s1 & s0 ;
Y<=A WHEN S="1110" ELSE
B WHEN S="1101" ELSE
C WHEN S="1011" ELSE
D WHEN S="0111" ELSE
‘1’;
END BHV;

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Origin www.cnblogs.com/lhkhhk/p/11779719.html