VHDL sequential logic devices study notes

1. trigger design

1.1 Basic D flip-flop design

The D flip-flop into substantially three ports: a signal input terminal D, the signal output terminal Q, and a clock input CLK.
Its operating characteristics: clock rising edge the moment, to acquire a signal from an input terminal to update the signal Q D output ports, the remaining time of the output signal D remains constant.
The following is the implementation code:

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DFF1 IS
	PORT(
	CLK,D	:	IN STD_LOGIC;
	Q		:	OUT STD_LOGIC
	);
END DFF1;

ARCHITECTURE BHV OF DFF1 IS
SIGNAL Q1	:	STD_LOGIC;
	BEGIN
	PROCESS(CLK,D)	BEGIN
	IF CLK'EVENT AND CLK='1'
		THEN Q1<=D;
	END IF;
	END PROCESS;
	Q<=Q1;
END BHV;

The final simulation results as shown in FIG.

1.1.1 several different trigger rising detection method

1. And use the event logic and function combination

CLK'EVENT AND CLK='1'

2. More insurance combination logic and event +

CLK'EVENT AND (CLK='1') AND (CLK'LAST_VALUE='0')

3. lastvalue functional form

CLK='1' AND CLK'LAST_VALUE='0'

4. rising_edge () function in the form of

IF RISING_EDGE(CLK)

1.2 with asynchronous reset D flip-flops clock enable

As the name suggests, it is more basic than the two input terminals of D flip-flop: asynchronous reset terminal RST and a clock enable terminal EN. For asynchronous reset terminal of the RST, as long as the input is "1", D flip-flop output terminal immediately cleared; the clock enable terminal EN, which is only "1", D flip-flop receiving a signal to clock rising edge, of generating a signal output port updated. Codes are as follows:

library ieee;
use ieee.STD_logic_1164.all;
entity dff2 is
port (
  D,CLK,EN,RST    :   IN std_logic;-- EN时钟使能  RST异步清零
  Q              :   OUT std_logic
) ;
end dff2;

architecture behav of dff2 is

  signal Q1   :   std_logic;

begin
reg : process( RST,EN,CLK,D )
begin
  if RST='1' then --触发器被清零
      Q1<='0';
      elsif EN='1' then
          if (CLK'EVENT AND CLK='1') then
              Q1 <= D;
          end if ;
  end if ;
end process ; -- reg
Q <= Q1;
end behav ; -- behav 

This section there are two questions, follow-up left to resolve:

• process sensitive variable table of sensitive variables, how to select it?
  The internal process to determine variables that appear in the statement, variable assignment symbol on the right side are included in sensitive variable table.
• There is about a 10ns delay is reasonable to do the simulation?
  reasonable!

1.3 Control synchronous reset D flip-flop

As the name suggests, the trigger comprising four input ports, the signal input terminal D, a clock signal CLK, a clock enable signal EN and a synchronization reset terminal RST, "RST = 1" only when the signal arrives at the rising edge until cleared in order to play the role of .
We should pay attention to two points:

• A clock synchronization signal is placed within the edge detection (below), the asynchronous signal is placed outside the edge detection clock (or more).
• Else statement appears indicating that the determination is affirmative statement is complete, instantiated in a combinational logic device determines if statement.

The following is the implementation code:

library IEEE;
use IEEE.std_logic_1164.all;

entity dff3 is 
port(
	RST,EN,CLK,D	:	in  std_logic;
	Q				:	out std_logic
);
end dff3;

architecture behav of dff3 is
	signal Q1	: 	std_logic;
	
	begin ---千万不要忘记architecture里的begin！
	reg:process (CLK,EN)	begin
	if (CLK'event and CLK='1' and EN='1') then --外部的if语句是不完整的，构成了时序逻辑器件
		if RST = '1' then --内部的if是完整的，构成了一个多路选择器
			Q1<='0';
			else --加上了else肯定是完整的判断语句
				Q1 <=D;
		end if;
	end if;	
	end process;
	Q <= Q1;
end behav;

Simulation results is as follows:

2. The latch design

2.1 Basic latch

The basic latch port components:

• Inputs: a clock signal CLK and the input signal D
• Output Ports: Output signal Q

The basic latch operating characteristics: when CLK = '1', the output signal Q is equal to the input timing signals D, when CLK = '0', the output signal Q remains.
Codes are as follows:

library IEEE;
use IEEE.std_logic_1164.all;

entity LTCH1 is 
	port(
		CLK,D	:	in  std_logic;
		Q		:	out std_logic
	);
end LTCH1;

architecture bhv of LTCH1 is 
signal Q1		:	std_logic;

begin
	reg:process(CLK,D)	begin
		if CLK='1' then
			Q1 <= D;
		end if;
	end process;
	Q <= Q1;
end; --bhv

Simulation waveforms as follows:

2.2 clear control latch containing

3. counter design

3.1 Simple addition of four binary counter

3.2 decimal addition counters with synchronous load and asynchronous reset function

4. Design of the shift register

The experimental subject

1) with a count enable design, the carry output, and synchronous preset number cleared to 0 by a two decimal counter

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity CNT20 is
  port (
	CLK,RST,EN,LOAD	:	in std_logic;-- 时钟信号、同步清零信号、计数使能信号、预置数信号
	DATA			：	in std_logic_vector(4 downto 0);--预置数信号
	DOUT			:	out std_logic_vector(4 downto 0);--计数输出
	COUT			：	out std_logic--进位输出
  ) ;
end CNT20;

architecture bhv of CNT20 is
	signal Q		:	std_logic_vector(4 downto 0);
begin
	REG : process( CLK,RST,EN,LOAD )
	begin
		if CLK'EVENT and CLK='1' then
			if RST='0' then	Q <= (others=>'0');-- 同步清零
			elsif EN='1' then
				if LOAD='0' then Q <= DATA;--采用低电平进行预置数
				elsif Q<19 then
					Q <= Q + 1;--未达到进位条件则进位
				else
					Q <= (others=>'0');--手动清零
				end if ;
			end if ;			
		end if ;
	end process ; -- REG

	COM : process( Q )
	begin
		if Q="10011" then --20进制计数到19
			COUT <= '1';
		else
			COUT <= '0';	
		end if ;
	end process ; -- COM
	DOUT <= Q;
end bhv ; -- bhv

2) design and implement an 8-bit binary counter with asynchronous clear and the count enable increased 0

3) design and implement a band enable count, the carry output, and asynchronous preset number is cleared to 0 in an increase / decrease of an 8-bit binary counter

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity CNT_8 is
  port (
	CLK,RST,EN,LOAD	:	in std_logic;-- 时钟信号、异步清零信号、计数使能信号、预置数信号
	DATA			：	in std_logic_vector(7 downto 0);--预置数信号
	DOUT			:	out std_logic_vector(7 downto 0);--计数输出
	COUT			：	out std_logic--进位输出
  ) ;
end CNT_8;

architecture bhv of CNT_8 is
	signal Q		:	std_logic_vector(7 downto 0);
begin
	REG : process( CLK,RST,EN,LOAD )
	begin
		if RST='0' then	Q <= (others=>'0');
			elsif CLK'EVENT and CLK='1' then
				if EN='1' then
					if LOAD='0' then Q <= DATA;
						else
							Q <= Q + 1;
					end if ;
				end if ;			
		end if ;
	end process ; -- REG

	COM : process( Q )
	begin
		if Q="11111111" then --
			COUT <= '1';
		else
			COUT <= '0';	
		end if ;
	end process ; -- COM
	DOUT <= Q;
end bhv ; -- bhv

Note that, since the 8-bit counter to count up all the bits, so the need to manually set the highest count bit is cleared jump.

4) Design of six string into and out Shift Register (over the use automatic data loading)

--串行输入并行输出
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SHIFT6_LEFT is
  port (
	CR,CLK,SHIFT    :   IN STD_LOGIC;  --清零信号、时钟信号、串行输入信号
	Y               :   OUT STD_LOGIC_VECTOR(5 DOwNTO 0)   --并行四位输出
	) ;
end SHIFT6_LEFT;

architecture A of SHIFT6_LEFT is

	signal TEMP_DATA    :   STD_LOGIC_VECTOR(6 DOWNTO 0); --共计7位，增加一位作为状态位

begin

REG1:process( CLK ) --状态位"011111"工作特性的设定
begin
	if CLK'EVENT AND CLK='1' then
		if CR='0' then--信号清零
			TEMP_DATA<="0000000";
			elsif TEMP_DATA(6)='0' then--状态位重载    --此句更改了TEMP_DATA
			--默认信号初始值都为0 (一般会先存在CR信号对TEMP_DATA进行清零)
				TEMP_DATA<="111110" & SHIFT ;
				else
					TEMP_DATA <= TEMP_DATA(5 DOWNTO 0) & SHIFT ;--信号左移：串行输入一位 & 高四位右移
		end if ;
	end if ;
end process ;


REG2:process( TEMP_DATA ) --并行输出时刻的设定
--每 移动一位\状态位重载 检测一次
begin
	if CLK'event and CLK='1' then
	   if TEMP_DATA(6)='0' then --输出状态位到达
		   Y <= TEMP_DATA(5 DOWNTO 0);
	   --else
		   --Y<="0000";
		end if ; 
	end if ;
end process ;
end A ;  

5) Design of the string 6 is incorporated Shift Register

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SHIFT6_RIGHT is
  port (
	CR,CLK    		:   IN STD_LOGIC; 
	SHIFT			:	IN STD_LOGIC_VECTOR(5 DOwNTO 0);
	Y               :   OUT STD_LOGIC   
	) ;
end SHIFT6_RIGHT;

architecture A of SHIFT6_RIGHT is

	signal TEMP_DATA    :   STD_LOGIC_VECTOR(11 DOWNTO 0);
begin

REG1:process( CLK )
begin
	if CLK'EVENT AND CLK='1' then
		if CR='0' then
			TEMP_DATA<=(others=>'0');
			elsif TEMP_DATA(0)='0' then 
				TEMP_DATA<=SHIFT & "011111";
				else
					TEMP_DATA(10 DOWNTO 0) <= TEMP_DATA(11 DOWNTO 1);
		end if ;
	end if ;
end process ;
Y <= TEMP_DATA(6);
end A ;  

6) Design of the string into the bit string 6 Shift Register

7) Design 6 incorporated in and out Shift Register

6. VHDL language writing specifications

I present a few excerpts in need of improvement, it is understood VHDL writing habits:
(full version Reference: VHDL writing specifications )

• Entity structure name, port signal, identifying constants uppercase; Similarly, variable represents the general signal using the first letter capitalized.
  
• VHDL reserved words in lowercase
• Multi-bit signal are described using downto
• When you call the library IEEE, IEEE uppercase, lowercase rest
  
• Each signal, variables, constants, and define the port should have a comment
• Use between process "--------" separated, if more than one process is to achieve a functional module, used between functional modules "- ********" to separate.
• To align the port name. To align the colon, in, or out generic be aligned, to define the alignment vector.
• Some common abbreviations signal