EDITORIAL words
In many cases , we need to collect data to get stored until needed time to re-call. If this is the case, then ask our memory must be readable and writable. In this section, we dream wing brothers and study together on FPGA writable memory IP core -RAM used.
Project requirements
Design of a RAM controller responsible for the RAM read and write operations, data is first written into RAM , and then read all the data. If the data is written and read exactly the same, that we correct operation and design.
Steps
On the right side of the IP core search field, type RAM , locate and double-click on the menu bar [ RAM : 1-PORT ]
Select the type of language Verilog , and name, click [ OK ]
Set ram memory depth and the number of bits of each storage space, and then click [ NEXT ]
The [q output port] in front of the hook to cancel (if not canceled will be generated at the output port register, the output is belated, here we do not need it belated), and then click [NEXT]
Continue to click [ NEXT ] until the following screen, select my_ram_inst.v , click [ Finish ] to complete the ram settings
Top-level architecture design
RAM is a read-write memory, we use a control module to the ram write data, then read out.
Module Features
| Module name |
Functional Description |
| Ram_control |
Ram controller, read and write to my_ram |
| My_ram |
ram memory IP core |
| ram |
Top-level module system, responsible for sub-module cascade |
. 5 . . 3 . 6-port and described interconnector
Top-level module port description
| Port Name |
Port Description |
| Clk |
System clock input |
| Rst_n |
System reset |
| q |
Data output |
Internal wiring system introduced
| Connection name |
Cabling instructions |
| addr |
Address signal generated Ram_control |
| data |
Ram_control generated data |
| wren |
Ram_control generating write control signals (write high level, a low level reading) |
5. 3.7 Code Explanation
Ram_control code modules
| /**************************************************** * Engineer: Dream Brother Wing * QQ : 761664056 * The module function: generating control signals and data **************************************** ************* / 00 module ram_control ( CLK 01 , // system clock input Rst_n 02 , // system reset WREN 03 , // read and write signals Addr 04 , // address signal 05 data // valid data 06 ); 07 // module input 08 INPUT CLK ; // system clock input 09 INPUT RST_N ; // reset 10 // module output 11 output reg wren; //读写信号 12 output reg [7:0] addr;//地址信号 13 output reg [7:0] data;//有效数据 14 //定义中间寄存器 15 reg state; //定义状态寄存器 16 17 always @ (posedge clk or negedge rst_n) 18 begin 19 if (!rst_n) // 复位时，将所有的输出清零。 20 begin 21 wren <= 0; 22 addr <= 0; 23 data <= 0; 24 state <= 0; 25 end 26 else 27 begin 28 case (state) 29 0 : begin 30 if (addr < 255)//使地址在0到255之间，让写信号有效 31 begin 32 addr <= addr + 1; 33 wren <= 1; 34 end 35 else 36 begin 37 addr <= 0;//转到下一个状态，让地址清零，让读信号有效 38 state <= 1; 39 wren <= 0; 40 end 41 42 if (data < 255)// 给有效数据，使数据在0到255之间 43 data <= data + 1; 44 else 45 data <= 0; 46 47 end 48 49 1 : begin 50 if (addr < 255)//使地址在0到255之间，让读信号有效 51 begin 52 addr <= addr + 1; 53 wren <= 0; 54 end 55 else 56 begin 57 state <= 0; //转到0状态，地址清零 58 addr <= 0; 59 end 60 end 61 62 default : state <= 0; // 如果系统不稳定的时候直接进入0状态 63 64 endcase 65 end 66 end 67 68 endmodule |
在本模块中，数据和地址的数值大小是一样的。
Ram的顶层代码
| /**************************************************** * Engineer : 梦翼师兄 * QQ : 761664056 * The module function:顶层模块，负责连接各子模块 *****************************************************/ 00 module ram ( 01 clk, //系统时钟输入 02 rst_n,//系统复位 03 q //输出数据 04 ); 05 // 系统输入 06 input clk; //系统时钟输入 07 input rst_n;//系统复位 08 // 系统输出 09 output [7:0] q;//输出数据 10 //定义中间连线信号 11 wire wren; //定义写信号 12 wire [7:0] addr;// 定义地址信号 13 wire [7:0] data;//定义中间数据 14 // 调用ram_control 15 ram_control ram_control ( 16 .clk(clk), //系统时钟输入 17 .rst_n(rst_n), //系统复位 18 .wren(wren), //读写信号 19 .addr(addr), //地址信号 20 .data(data) //有效数据 21 ); 22 //调用IP核--ram 23 my_ram my_ram_inst ( 24 .address ( addr ), // 地址信号 25 .clock ( clk ), // 系统时钟 26 .data ( data ), // 输入数据 27 .wren ( wren ), //读写信号 28 .q ( q ) //输出数据 29 ); 30 31 endmodule |
本模块只负责连接各个子模块，没有任何的逻辑。代码编写完毕以后，查看RTL视图如下：
由RTL视图可以看出，电路综合以后的结果和我们所设计的系统框图一致，接下来编写测试代码如下：
| /**************************************************** * Engineer : 梦翼师兄 * QQ : 761664056 * The module function:对ram进行测试 *****************************************************/ 00 `timescale 1ns/1ps //时间单位和精度定义 01 module ram_tb; 02 //系统输入 03 reg clk; //系统时钟输入 04 reg rst_n; //系统复位 05 //系统输出 06 wire [7:0] q; //输出数据 07 08 initial begin 09 clk = 1; 10 rst_n = 0; 11 # 200.1 12 rst_n = 1; 13 end 14 15 always # 10 clk = ~clk; //50MHz时钟 16 17 ram ram ( 18 .clk(clk), //系统时钟输入 19 .rst_n(rst_n), //系统复位 20 .q(q) //输出数据 21 ); 22 23 24 endmodule |
仿真分析
复位结束之后，写信号有效，同时给出数据和地址。Ram的q端在写的过程中也会进行慢一拍的输出，这不是错误，这是由Ram内部结构决定的。
注：写数据的过程中，q端也会输出，这是由altera RAM IP核的功能决定的，此处不需要深究。
当写完数据之后，进行读（写信号拉低），同时给出地址，ram在下一拍给出对应地址中的数据。
经过上述的分析，证明我们的ram应用正确。