This switched power development ring
To provide power for the chip on the PCB (printed circuit board) is not a simple task. In the past, fine traces by connecting the IC to the supply and ground on the line, these traces not take up much space. When the chip speed rises, it is necessary for them with low-impedance power supply, such as with a power source layer on the PCB. Sometimes, only need a power supply layer and a four-layer circuit board, the power supply can be solved most of integrity issues. In addition to the power supply layer, it may also be coupled to each IC, the power supply to solve the problems in the design complicated.
Now, however, the PCB space (as well as costs associated with your schedule) is very tight, these problems have had an impact on the power supply. Dave Kohlmeier, senior director of Mentor Graphics simulation and modeling products, said: "consumer devices and portable devices in order to save costs and use fewer PCB layers, but they are above the IC but require more voltage levels." These issues not only affect portable products, industrial products, there are space constraints (Figure 1). Modern circuit of a cellular base station to be installed in a small box on the antenna, the antenna is generally located within the 19-inch rack architecture.
In the high-volume consumer products and automotive products, the cost is a key factor. Put a bunch of unwanted capacitance may be the PCB, it is definitely unacceptable. To be successful, it will shorten the design cycle to a weekly in months, not years. Now, it is impossible only to repair and optimize the power and ground and take the time to the PCB over again.
For the modern design of the power electronics system is a daunting challenge. DDR memory working at 1600Mbps, 2200Mbps and will soon run into quadruple mode. Worse, it is a single-ended output, means that your power supply system must deal with unexpected challenges of supply current. The device may also have a digital gate switch, power integrity engineers such as simultaneous switching noise characterization. Serial communication with hard power requirements. 802.3ba standard Ethernet data rate is 40Gbps and 100Gbps.
Modern digital chip operating voltage of less than 1V, which means that even millivolt of noise can also cause problems associated with the data. More than just the chip will increase and cause power drop or overvoltage problem statistically. Your system may be weeks or even months are operating normally, but at some point for all digital circuitry while the switch has caused reboot the system. These power integrity problems are difficult to detect. Single supply system integrity issues may affect other chip-chip system, leading to restart. National Semiconductor's analog applications engineer Paul Grohe said: "Even if the power loss nanosecond also make the system unreliable." Steve Patel Ansys company's signal integrity product manager, said the key is to design as much as possible to reduce the power supply reliability noise, means that digital systems engineer must know how to simulate even RF design concept.
The power supply system engineer know, must have a power supply system impedance (FIG. 2) is low, but the concept is the analog engineer, an analog IC feet noise power as small as possible. Different from the digital chip, an analog chip noise threshold does not exist. PSRR (power supply rejection ratio) specification of the number of power supply noise will penetrate to the output pin of the device. Digital systems engineers must now deal with the same power supply noise problem.
Brad Brim Sigrity product marketing manager, providing power for the chip power distribution network requires a low equivalent inductance: as 0.01 N on the core voltage, for I / O supply of 1nH. He noted that the power supply layer couple noise into the signal. In some cases, a signal line on the cloth between the two strata 15mV of noise. When the layout of the art between the power and ground planes laying the same signal, which noise of 45mV.
Power integrity tools can make a decided optimize the design. When you do layout optimization, you can not use decoupling empirical method. Patel said the company Ansys software can help you determine the capacitance of the number, type and cost. These tools can tell you the effect of changing the distance between the layers. For example, TechDream President and founder said Yoshi Fukawa, NEC Corporation's PI (power integrity) Stream can add or remove the capacitance, capacitance change shape and layers, as well as changing the distance between the power and ground planes, to help you impedance obtained their goal.
Mentor's Kohlmeier said: "You can do what-if experiments with a CAD file of this retry this is much faster than the hardware virtual prototypes of value..." Therefore, it is important to use simulation software, so you can design make critical decisions early stage. Capacitance change position, the number of capacitors and other variables may not affect other sectors, but in order to improve the inter-layer capacitance while reducing the distance between the layers, it will affect the entire design team (Figure 3). Sanmina-SCI modern manufacturing method of the patent, may be devised between 4mil dielectric layer thickness increases the capacitance between the layers.
way of solving the problem
Kohlmeier said power integrity simulation than many engineers expected to be more difficult, because you must consider each capacitor, vias, and the structure of the power layer connections. He pointed out that two levels of connection vias will reduce the impedance of the supply network, so it is just as important and capacitance. With different power integrity, signal integrity will generally involve some traces, oscilloscope integrity can be measured in the time domain signal. Use Port 1 to Port Z11 impedance curve 1, power integrity simulation of the impedance can be obtained in the frequency domain. To understand impedance issue a power layer, you need a VNA (vector network analyzer), it is difficult to use. Simulation is measured supplement, not replace, they will provide important information about the properties of the PCB prior to manufacturing. Sigrity's Brim said: "No matter how fast your simulation software, but also fast single measurement." However, he pointed out, you have to have a good PCB has been manufactured to make rapid measurements.
You must believe IC designers work done, I believe that the chip used no power integrity issues. Patel said Ansys company, "IC and bonding wires are not critical power integrity," as IC power supply pin and the bonding lines are connected in parallel (FIG. 4). Mentor Graphics HyperLynx company's engineering director Steve Kaufer, believes that the lack of technical knowledge to avoid power integrity and signal integrity problems layout engineers, it often is the root of the problem.
Power integrity software can help you solve the problems of DC and AC, additional holes between the power and ground planes are RF waveguide. To address current issues, we must ensure that the PCB layers may carry current to be provided. To deal with communication problems, we must ensure that the system can provide the power required for the current fast-changing modern chips. Finally, note that the waveguide may be non-intuitive behavior. RF issue is important in the defense EMI (electromagnetic interference) problems, it will make your board can not be certified by FCC (Federal Communications Commission). If the design uses a large board, it is important to use the simulation, a large plate surface will resonate. If your board RF is emitted from the cavity between the layers, the simulation with the appropriate software can help EMI engineers to solve such problems. Correction capacitor laying method may be around the edges of the circuit board. Sun Microsystems, Inc. has a Patent 6,727,780, which uses a resistor in series with the capacitor, so that RF energy can be absorbed at the edge of the board, and not reflected back into the structure.
Digital chip requires a large current, which may cause problems DC power supply. FPGA and other digital chips require a variety of power supply voltage, therefore, the power supply layer must be divided to provide a plurality of voltage rails. There are hundreds of digital chip pins, it requires hundreds of vias that can cover a wide area of the copper foil power and formation. Must be ensured on the copper foil chosen for these layers, the current density remains below a reasonable value (FIG. 5).
High DC currents can also cause thermal problem. The temperature coefficient of copper is 0.4% / ° C, i.e. the temperature is increased 25 ° C, a 10% increase in resistance. This increase in resistance occurs under heavy load, then reliability is critical. Also increase resistance to raise the temperature, reducing the life of the circuit board components.
Once the copper foil provided with a sufficient DC load, the design should pay attention to the AC power supply layer (FIG. 6). Power integrity simulation to check the return current flows through the power supply layer position. In operation, a digital chip to obtain the current intensity is different, and the change in nanoseconds. The power supply must have sufficiently low impedance can vary with the current (expressed as di / dt, i.e., the derivative of the current / time derivative), so as not to cause a large change in power supply voltage generating chip pins. Since di / dt will emit electromagnetic energy, these offsets may cause EMI problems. Thus, signal integrity, EMI and power integrity compliance are interrelated. Without simulation, your design is crosstalk and other problems seem baffling between the holes may appear too.
Software Select
a power supply network of the actual geometry of its performance is so important that most software vendors have used field solver technology in its power integrity tools.
These tools should give you a quick answer and accurate results. RF-IC and system designers typically use a full wave field solvers, the solution of Maxwell's equations 3D. However, 3D field solver takes a long time to get results, especially when used in relatively large physical item, such as a PCB board. Therefore, the integrity of the power suppliers in their power integrity tools designed hybrid solver technology. When solving traces, these tools use a transmission line theory using fast 2D solver technology. Plane during simulation, using a finite element tool technology of 2D or 2.5D. In some cases, the software can use a set of parameters of the total capacitance and inductance element model for modeling vias. To obtain more accurate results, the tool may use a pair of through holes full wave 3D solver.
It is also possible to adopt a full-wave simulation results solver to 3D structure, such as connector pins and other mechanical devices in the power path. Software vendors still own tools into the thermal analysis. It may be used alone, or the heat output to a dedicated message thermal analysis tools, such as the Mentor Graphics FloTherm, which is a CFD (computational fluid dynamics) of the 3D simulation environment. Mentor's HyperLynx simulation tools can do their own thermal analysis, and outputs the result to the FloTherm, so that you can build the entire system or a single chassis thermal performance model.
Agilent's re-developed its own ADS (Advanced Design System) Momentum products, it can have very many vias for the power and ground planes to provide simulation results. It is also used to power a small layer design traces. The MOM (Method of Moments) is the fastest simulation method for a multilayer structure, capable of solving the full 3D games, including all entries of Maxwell's equations. This scheme allows a full-wave high-frequency effects of Faraday's law, and the Maxwell equations for the Ampère substitution increased current term. MOM level with large simulation time-consuming, so the Agilent invented a number of algorithms can reduce the time needed to obtain accurate results. Agilent's high-speed digital product owner Colin Warwick said tool uses a tree / Collaboration tree (tree / co-tree) method can be used until the DC.
Further members may be planar, lumped parameter analysis method. NEC's software will PIStreamn plane modeled as lumped matrix, to apply to other engines and the use of Spice lumped-parameter analysis technique. For a plane, the software uses the PEEC (PEEC) technique, generates a RLGC (resistor / inductor / conductivity / capacitance) equivalents. The software also creates a lumped parameter model (FIG. 7) through the cavity formed between the aperture and the power and ground planes. Software also uses a series the RLC (resistance / inductance / capacitance) model as a decoupling capacitor model, the model considers the parasitic resistance and the parasitic inductance of the capacitor and the resistance and capacitance fan-away lines and vias. You can build simulation run, rapid completion of the analysis of a single plate. When the setting change, the software will make a multilayer analysis taking into account all relevant plate surface.
In addition to physical simulation of the finished board structure, HyperLynx such software tools can do the early planning plane and decoupling circuit board layer structure. You can then run a quick analysis to obtain some of the concepts related to the transfer impedance and other variables. Giga Hertz technology has developed a faster engine Spice, integrate into the NEC the PDN (power distribution network) Expert in. These floorplanning tools can manually describe the schematic and PCB levels early in the design optimization capacitance. Thus, the plate surface can be obtained about the shape, size, stacked, and the concept of the number of capacitors.
Some PC world power integrity software vendors (such as Mentor Graphics and Cadence) own tools into the design flow. Although this does not eliminate the worry about all the tools provided by the vendor, but the power integrity simulation using a physical representation of the PCB, to become a geometric model. Sigrity and Ansys company can accept input Allegro, Mentor Graphics of PADS, Altium and Zuken and tools from companies such as Cadence's. Agilent's power integrity tools stems from its expertise in RF design. In addition to combination with ADS design tool, the company's software can also EMPro PCB input data from Cadence's Allegro. NEC customers will often be used in conjunction with the PIStream Zuken's PCB tool, but the software can accept input data in Cadence Allegro PCB and other software.
Although some engineers prefer their own board of process integration tools, but this Ansys simulation tools to get professional company also has some advantages. For example, the company's SI (signal integrity) Wave tool is similar to the company's Mentro Graphics HyperLynx, and PIAdvisor tools can help you delve into power integrity issues. The tool has a 3D solver for the simulation of vias. In addition, companies can also be used Ansys HFSS (High Frequency emulator system) tool, make full 3D simulation of physical problems, such as connectors, and other 3D geometries. Some customers will Ansys output signal integrity and power integrity tools tools HFSS lost to the same tools they use, the modeling of the chassis. In this way, they can evaluate EMI products. CST (computer simulation technology) EM Studio software pharmaceutically Gerber PCB input file, and may calculate the 3D IR (current / resistance) drop.
You must have the ability to choose the software needed. Many companies want you to separate signal integrity and power integrity issues, they assumed, once you substantially reduce the impedance of the power supply, it will focus on signal integrity. Problems of this embodiment, the power supply noise is noise and signal interact. To address this problem, Sigrity company allows you emulation effect of power supply noise on the signal integrity (Figure 8). The company CST Microwave Studio can also analyze noise propagation from the power plane in close proximity.
Expensive problem
Price Power Integrity software often makes inexperienced engineers stunned. A simple DC simulator could be $ 15,000, and includes a power integrity, signal integrity and complete system thermal solver, might cost $ 75,000. This figure seems high for the software, but should take into account the cost of power integrity failure. Reproduce a complex circuit boards, in the production and engineering may cost $ 5,000 or $ 10,000, but not in time to market cost is $ 10 million. Another consideration is that the system BOM (BOM) cost. If the power integrity software can save 50 cents on the capacitor, then to a high-volume product, it is possible to earn back the cost of power integrity software in a few months.
Ansys companies Patel found that in the past do power integrity, three engineers, signal integrity and EMI analysis are isolated from each other. Now, although it may still be an engineer to do EMI analysis, but this man must first do the work with a power integrity and signal integrity analysis of the people, they often share the same software. Sigrity's Brim pointed out, IBIS
(Input / output buffer specifications) Power 5.0 - ground
And data signals, so that noise associated software simulation model 5.0 supply pins may be output through the leak noise, similar to that of analog devices PSRR specification. All of these functions into a joint effect that allows you to have a well-designed and reliable product (Figure 9).
If you understand and know how to use these expensive tools, the status as an engineer will be doubled. For those who prefer CAD (computer aided design) software engineers, these tools are not difficult to learn. Mentor Graphics Corp.'s sales in many places offer free HyperLynx learning courses. If you have experienced other types of simulators, the learning power integrity tools basically no problem. Need to learn and understand the concept and the technical terms in the frequency domain, such as RF designers. If you increase the knowledge on the existing time-domain experience, you will be able to accept the most stringent design challenges and become a winner.
