This chapter references "ARM Cortex ™ -M4F Technical Reference Manual" -4.5 chapter SysTick Timer (STK), and section 4.48 SHPRx, which is described in detail STK This chapter profiles and register the SysTick. Because the core SysTick belongs CM4 peripherals, definition register and a partial library functions are implemented in this core_cm4.h header file. So when learning SysTick can refer to these two materials, one document, one source.
SysTick Profile
SysTick- system timer is a peripheral part of CM4 kernel, embedded in the NVIC. The system timer is decremented down to a 24bit counter, the counter counting each time the time of 1 / SYSCLK, we set the system clock SYSCLK generally equal to 180M. When the value in the reload register value is decremented to 0, the system timer generates an interrupt, the cycle in order.
Because SysTick belongs CM4 kernel peripherals, so all CM4-based microcontroller core of this system has a timer so that the software in CM4 microcontroller can be easily ported. System timer for operating the system in general, used for generating group, maintaining the operating system heartbeat.
register
| Register Name | Register Description |
|---|---|
| CTRL | SysTick Control and Status Register |
| LOAD | SysTick Reload Value Register |
| VAL | SysTick Current Value Register |
| CALIB | Calibration Value Register SysTick |
Table 18-2 SysTick Control and Status Register
| Bit segment | name | Types of | Reset value | description |
|---|---|---|---|---|
| 16 | COUNTFLAG | R/W | 0 | If the last read of this register, the SysTick has counted to zero, the bit is 1. |
| 2 | CLKSOURCE | R/W | 0 | Clock source selection, 0 = AHB / 8, 1 = the processor clock AHB |
| 1 | TICKINT | R/W | 0 | 1 = SysTick generated when the countdown to 0 SysTick exception request, 0 = 0 to the number of no operation. It may also be determined whether the counter is decremented to 0 by reading the flag COUNTFLAG |
| 0 | ENABLE | R/W | 0 | SysTick timer enable bit |
Table 18-3 SysTick Reload Value Register
| Bit segment | name | Types of | Reset value | description |
|---|---|---|---|---|
| 23:0 | RELOAD | R/W | 0 | When the countdown reaches zero, a value to be reloaded |
Table 18-4 SysTick current value register
| Bit segment | name | Types of | Reset value | description |
|---|---|---|---|---|
| 23:0 | CURRENT | R/W | 0 | Returns the value of the current reading of the countdown, then writing it to make clear, it also clears the COUNTFLAG marked SysTick Control and Status register |
Table 18-5 SysTick Calibration Value Register
| Bit segment | name | Types of | Reset value | description |
|---|---|---|---|---|
| 31 | NOREF | R | 0 | NOREF flag. Reads as zero. Indicates that aseparate reference clock is provided.The frequency of this clock is HCLK/8 |
| 30 | SKEW | R | 1 | SKEW flag: Indicates whether the TENMS valueis exact. Reads as one. Calibrationvalue for the 1 ms inexact timing is not knownbecause TENMS is not known. This can affectthe suitability of SysTick as a software real timeclock |
| 23:0 | TENMS | R | 0 | Calibration value. Indicates the calibration valuewhen the SysTick counterruns on HCLK max/8as external clock. The value is productdependent, please refer to theProduct ReferenceManual, SysTick Calibration Value section.When HCLK is programmed atthe maximumfrequency, the SysTick period is 1ms.If calibration information is not known, calculatethe calibration value required from thefrequencyof the processor clock or external clock |
Timing experiments SysTick
SysTick_Config () library function SysTick mainly arranged in three registers: LOAD, VAL and CTRL, comments on specific portions of the code to see. It also called firmware library function NVIC_SetPriority () to configure the system timer interrupt priority, the library functions are defined in core_m4.h, prototype is as follows:
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)IRQn < 0)
{
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] =
(uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
NVIC->IP[((uint32_t)(int32_t)IRQn)] =(uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}SysTick peripherals as part of the kernel, common peripherals with interrupt priority some differences, and there is no preemption priority and sub-priority claims. In STM32F429, core peripheral interrupt priority level of the peripheral core SCB register: SHPRx (x = 1.2.3) is configured. For a detailed description reference is SHPRx register "Cortex-M4 core Programming Manual" Chapter 4.4.8. Here we briefly introduce this register.
SPRH1-SPRH3 is a 32-bit register, but can only be accessed by byte, eight fields each control a peripheral interrupt priority core configuration. In STM32F429, only bits 7: 3 What four high active, low four is not used, so that the core peripheral programmable interrupt priority: 0 ~ 15, only 16 programmable priority levels, the smaller the value, the higher the priority. If the software is configured with the same priority, then according to their position number in the interrupt vector table to determine which priority size, the smaller the number, the higher the priority.
If you want to change the priority of the peripheral core, only need to modify a field corresponding to the following three registers.
In the system timer, configured priority (1UL << __NVIC_PRIO_BITS) - 1UL), wherein the macro __NVIC_PRIO_BITS is 4, then the calculation result is equal to 15, it can be seen at this time priority system timer provided in the peripheral core It is the lowest.
// 设置系统定时器中断优先级 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);