S3C2440 has two PLL (phase locked loop) is a MPLL, one UPLL. MPLL for the CPU and other peripheral devices, UPLL for USB. For generating FCLK, HCLK, PCLK three frequencies, three frequencies are used for different purposes:
1.FCLK clock signals provided by the CPU.
HCLK clock signal is provided to the AHB bus, Advanced High-performance Bus, mainly for high-speed peripherals, such as memory controller, interrupt controller, LCD controller, the DMA and the like.
DataSheet S3C2440 can be seen from the inside, S3C2440 clocked at 400MHz maximum support, but this does not mean necessarily work at 400MHz below, you can set the operating frequency of the CPU by setting MPLL, UPLL register.
Despite power (power-on) or a reset on the CPU (reset), MPLL began to enter the working state, but this time MPLL output (Mpll is) not as the system clock, but the use of an external clock signal or an external direct EXTCLK crystal as the system clock. Until MPLL software initialization register (rMPLLCON), after a valid value is written, the system began using MPLL output (Mpll is) as the system clock. Although many times we do not have to re-set MPLL register (rMPLLCON) new value, but in order to use the system as its output clock signal, the system software initialization section, or would like to write an effective rMPLLCON old values. Like this was the system in proper operating condition.
2.HCLK is a clock signal provided to the AHB bus, Advanced High-performance Bus, mainly for high-speed peripherals , such as memory controller, interrupt controller, LCD controller, the DMA and the like.
3. the PCLK clock signal provided to the APB bus, Advanced Peripherals Bus, mainly for low-speed peripherals , such as the watchdog, the UART controller , IIS, I2C, SDI / MMC , GPIO, RTC and SPI like.