S3C2440A memory controller provides a control signal to access memory external storage device needs.
S3C2440A includes the following features:
- Large / small end (selectable by software)
- Address Space: Each Bank has 128M bytes (a total of 1G / 8 th Bank)
- Large / small end (selectable by software)
- in addition to BANK0 (16 / 32) than all the other programmable BANK have access width (8/16/32 bit)
- a total of eight memory Bank
. 6 Bank of memory ROM, SRAM, etc.
remaining two memory Bank as ROM, SRAM, the SDRAM and the like
- Bank 7 fixed memory start address
-1 Bank variable memory starting address and the size of the programmable Bank
You can theoretically address space for 4GB
0x00000000-0x3FFFFFFF, 1G space externally addressable space ( can choose to start from NORFlash, or starting from the internal SRAM (i.e., the power to the internal 4KB copied before the CPU SRAM NANDFLASH) .
0x48000000-0x5FFFFFFF, sent to the internal processor
memory address
GPBCON Register Address: 0x56000010
GPBDAT Register Address: 0x56000014
remaining address space is not used
S3C2440 the external lead 27 address lines:
ADDR0 ~ ADDR26
. 8 chip select signal: nGCS0 ~ nGCS7
each signal corresponds to a nGCSx in Ban
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S3C2440 comprising GPA, GPB, GPC, the GPD,
the GPE, GPF in, the GPG, GPH, port 9 groups of GPJ
most multiplexing pins are
configurable through a corresponding register I / O mode
GPA corresponding control register: GPACON, the GPADAT
GPB corresponding control register: GPBCON, GPBDAT, GPBUP
most I / O may be configured as input, output mode or
other special features, and may choose whether to pull the interior.
A set of three major operating port registers, as example here to GPB
Control register
Registers and data registers pullup
