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Chapter VII of the memory controller
7.1 Overview
The memory controller is responsible for access to external memory , providing the correct control signal for the memory. The following is 1GB memory partition access FIG :
7.2 Functional Description
The memory controller functionality comprisingThree important mode of operation：
bank0Bus width is providednWAITPin operationnXBREQ/nXBACKPin operation
7.4 Memory Control register
Memory control register comprises:
- And wait control register bus width (
BWSOCN，32位) - Control register bank
- Refresh control register
- banksize register
- Register Mode Register Set