2.26-GNU Make Tutorial

• The following is a "follow me to write together Makefile" notes
• Learning objectives: the ability to write Makefile minor works can be read automatically generated Makefile CMake
  
• Make tool is an automated build tools, decided to write a script file can be compiled rule the whole project, such as which files to compile, after which files are compiled, the compiled file in any directory, and so on.
• Version of the book is 3.80, the local version is 3.81, showing that make tools for so many years have not been updated
• About compiled knowledge, the system had to learn the Dragon book "Compiler Principle"
• There are 3 examples of engineering and 8 C header file file, because there is no download, had speculated that the
• command.c    display.c    insert.c    search.c    files.c    utils.c  main.c  kbd.c
• defs.h  command.h  buffer.h
  
• The first acts of dependency, the second behavior command, the second line needs to begin with the Tab key
• We can also define "clean" has nothing to do with the compiler and other actions
• GNU Make and files can be automatically pushed to the back of the file dependencies command
• ".PHONY" explicitly indicates that the target is a dummy file, the file with the same name to avoid
• Add front command "-" role is: If the command is wrong, then ignore this error and continue to execute other commands
• Do not set the environment variable $ {MAKEFILES}
• Semicolon ";" is used to separate multiple command
• If the command is too long, use the backslash "\" Branch
• It features pseudo goal is always up to date, if there are dependent files behind will never be updated
• "? $" Means:
• "$ @" Means: a storage array target collection, which in turn kept the goal of all
• "$ <" Means: all the dependent target set
• gcc command: gcc -MM main.c automatically generated file dependency, the dependency need not stated in the Makefile (-M standard library header files will also include it)
• If you want the result of the application on a command to the next command, these two commands separated by a semicolon
• Traditional Makefile variable name is capitalized, but the case is now recommended with the variable name, variable avoid conflict and systems, accident.
• In general, the use of variable names should be this: $ {} parentheses entirely for even more security.
• Nature macro variable name, will first expand at run-time, the essence is the "extended"
• "=" And ": =" difference is: the former can later reference variable, which only previous references variables
• Goal variables: Set a local variable to a target, its range of action, and this rule is only in the associated rule, so its value is valid only within the scope, and will not affect the values ​​of global variables other than the chain rule
• Pattern variables: We can define the variable on all targets in line with a model, this variable is also a local variable
• Conditional expression: Make is calculated on the value of the conditional expression when reading Makefile, the equivalent of pre-compiled C language, so in conditional expressions are not made automation variables (such as "$ @"), because automation variables at runtime it is there, and does not allow the entire conditional statement into two parts in different files.
• Function comprising: a string manipulation functions; filename operation functions; the foreach function; if, call, origin, shell function, the control Make error, warning function
• Make the run: the development of Makefile, setting goals, etc.
• Make parameters: if a plurality of path parameter, then the backward path in front of the path as a relative path, and to last directory as the directory formulation.
• The number of the command is run at the same time: -j --jobs
• Make implicit rules: If you want to generate the target you need to use implicit rules, you need to do is not to write this goal rule
• Implicit rules is in order, if you explicitly set the rules, but the rules still ahead of "hidden rules" more forward rules are more frequently used, so as implicit rules take effect.
• There are two implicit rules, "model rules" and "Rules suffix"
• Suffix rule: as long as the file suffix is ​​included in the "suffix list", then these implicit rules will take effect.
• Implicit variable rules, dichotomous variables and variables on the command about the parameters.
• CPP is the C preprocessor
• C ++ source code suffix * .cc
• In fact, the library file is packaged files * .obj or * .o intermediate file, in UNIX, a static library * .a, the dynamic library * .so.
• Key - pattern rules
• Usage patterns rules to define an implicit rule
• "%" Means that the representation of one or more of any character. You can also use "%" in the project dependent, but dependent on the value of the project, depending on its target. This means that the goal of the "%" value determines the value of the dependent targets
• %.o : %.c ; <command ......>
• Once dependent on target in the "%" mode is determined, then, make would be required to match all the filenames in the current directory
  
• Key - Automatic variables!
• Automation variables
• "$ @" Indicates the value of all the goals one by one, "$ <" indicates that all targets depend on value one by one.
• $ @ Target file representation rule set.
• $@
• Target file representation rule set. In the model rules, if there are multiple targets, then "$ @" is the match
• Collection target schema definitions.
• $%
• Only when the target is a library file, representing the target member name rules. For example, if a goal is "foo.a
• (Bar.o) ", then" $% "is" bar.o "," $ @ "is" foo.a ". If the target is not a library file (Unix
• Under is [.a], under Windows is [.lib]), then its value is empty.
• $<
• Rely first goal in the name of the target. If the target is dependent mode (ie, "%") is defined, then the "$ <" will
• Model is in line with a series of file sets. Note that it is taken out one by one.
• $?
• The new set of targets all dependent than the target. Separated by a space.
• $^
• All rely on a set of goals. Separated by a space. If there are several duplicate in dependence target, that this variable
• Removes duplicate dependent on target, leaving only one.
• $+
• The variables like "$ ^", is all dependent on the target collection. It does not just remove duplicate dependencies goal.
• $*
• This variable represents the target mode "%" section and before. If the goal is "dir / a.foo.b", and the target of
• Mode is "a.%. B", then "$ *" value is the "dir / a.foo". This variable file names associated structure than
• It is more than. If the target is not defined mode, then "$ *" it can not be derived, however, if the target file
• Make suffix is ​​identified, then the "$ *" is in addition to that part of the suffix. For example: If the goal is "foo.c", because
• ".C" is a make can be identified by the suffix, so "$ *" value is "foo". This feature is of GNU make,
• Probably not compatible with other versions of make, so you should try to avoid using "$ *", except in implicit rules
• Or static mode. If the goal is to make the suffix can not be identified, then "$ *" is null.
• When you want to rely only on the updated files to operate, "$?" Is useful in an explicit rule, for example, suppose you have
• A library file called "lib", which is updated by several other object files. Compare then the object file packed
• Efficient Makefile rules are:
• lib : foo.o bar.o lose.o win.o
• ar r lib $?
• In the automatic variable amount to the listed above. Four variables ($ @, $ <, $% $ *) only when there is a file extension
• Pieces, while the other three values ​​is a list of files. These seven automation variables can also obtain the file or directory name in the current
• File names conform to the schema directory, just with the "D" word or "F". This is the old version of GNU make features,
• In the new version, we use the function "dir" or "notdir" can be done. The meaning of "D" is the Directory, it
• Is a directory, the meaning of "F" is File, the file is.
• The following are seven variables, respectively, for the above plus "D" or "F" means:
• $(@D)
• Said, "$ @" catalog section (not to slash as the end), if the "$ @" value "dir / foo.o", then "$ (@ D)"
• It is the "dir", and if "$ @" does not contain a slash, then its value is "." (Current directory).
• $(@F)
• He said, "$ @" portion of the file, if the "$ @" value "dir / foo.o", then "$ (@ F)" is "foo.o", "$ (@ F)"
• Equivalent function "$ (notdir $ @)".
• "$(*D)"
• "$(*F)"
• Similarly as described above and also take part directory and files of the file. For the example above, "$ (* D)"
• Return "dir", and "$ (* F)" returns "foo"
• "$(%D)"
• "$(%F)"
• Indicate the file directory part and part of the function package file members. This is tantamount to "archive (member)" shaped
• Type of target in the "member" contains a different directory useful.
• "$(<D)"
• "$(<F)"
• Represent directories and files in part dependent part of the file.
• "$(^D)"
• "$(^F)"
• Represent the directory section and all dependent files section of the file. (Non-identical)
• "$(+D)"
• "$(+F)"
• Represent the directory section and all dependent files section of the file. (Which may be the same)
• "$(?D)"
• "$(?F)"
• Respectively, and the file directory part depend partially updated file.
• Finally, I would remind you that for "$ <", in order to avoid unnecessary trouble, we'd better give back that $
• A specific character with parentheses, such as "$ (<)" than, "$ <" is better.
• We have to note that these variables in order to use only the rules of, and generally are "explicit rules" and "Static
• Pattern rules "(see previous" writing rules "chapter). It does not make sense in implicit rules.