Nand flash chip model Samsung K9F1208U0B, the data storage capacity of 64MB, using the storage management block page. 8 I / O
Pins act as data, address, multiplexing port command.
Internal memory chip layout and characteristics of the storage operation
A Nand flash as a device (device), which is a hierarchical data store: a device (Device) = 4096 block (Blocks)
1 (Block) = 32 pages / lines (Pages / rows); p is the same meaning as the row, not the same name
1 (Page) = 528 bytes (Bytes) = data block size (512Bytes) + OOB block size (16Bytes)
In each page, the last 16 bytes (also called OOB) for the command has completed Nand Flash by setting a state, the remaining 512 bytes is divided into a first half and a second half. You may command 00h / 01h / 50h, respectively by Nand Flash front half, rear half, positioning the OOB directed by each first address pointer built Nand Flash.
Store operations Features:
1. The minimum unit is the block erase operation.
2. Nand Flash chips every (bit) can only be changed from 1 to 0, not from 0 to 1, so before you want to write to some of the corresponding
Block erase (erase block that is obtained corresponding to 1 bit becomes full).
3. OOB portion sixth byte (i.e., 517 bytes) is a bad block flag, if the bad block is not at FF, or a bad block.
4. In addition to the sixth byte OOB, typically at least the first three bytes of OOB Nand Flash storage hardware ECC code (ECC code on a hardware controller Nandflash see section).
Important chip pin function
I / O0I / O7: multiplexed pins. It can input data to the nand flash chip, address, command, and nand flash operation and the output data
status information.
CLE (Command Latch Enable): command latch enable
ALE (Address Lactch Enable): Address latch enable
CE: chip select
RE: read enable
WE: write enable
WP: During the write or erase, write protection provided
R / B: Read / Busy Output
Addressing
Samsung K9F1208U0B Nand Flash inner sheet 26 addressed using address format. Start from bit 0 through in four I / O0-I / O7
Transmission, and chip address. Specific meaning as follows:
Bits 0-7: byte in the upper half, the lower half of the offset address and OOB
8: 0 represents the value of the first 256 bytes in an addressable
After the value represents a 256 byte address bits 9-13: addressing of page
Bits 14-25: When the block address when transmitting the address, from the start bit 0
Nand flash Main features detailed command
Nand Flash command execution is performed by the command word to a command register Nand Flash controller.
Nand Flash half cycle command is executed, each command has one or more execution cycles per execution cycle has a matched code represents the circumferential
On the action to be performed.
The main commands are: Read 1, Read 2, Read ID, Reset, Page Program, Block Erase, Read Status.
Details are as follows:
- Read 1：
Function: Represents the Nand flash memory to be read in the first half of a page, and the built-in pointer is positioned to the front half of the first byte.
Command Code: 00h
- Read 2：
Function: Represents the second half of Nand flash will be read in a page memory, and the built-in pointer to locate the first byte of the latter half.
Command Code: 01h
- Read ID：
Function: ID number read command code Nand flash chips: 90h
- Reset: Function: reset IC. Command code: FFh
- Page Program：
Function: page programming commands for write operations.
Command Code: firstly writing 00h (A zone) / 01h (B zone) / 05h (C region), it indicates the writing area; 80h re-writing start programming mode (write mode), then
Down the write address and data; last written 10h the end of the programming.
- Block Erase
Function: block erase command.
Command code: 60h is first written into the erase mode, then the address input block; Next D0h written, indicating the end of erase.
- Read Status Function: internal status read command register value. Command Code: 70h