EMC issue in the main PCB design re-explain the following aspects (focus on explaining wiring):
1, layout
2, wirings (crosstalk, impedance matching)
3, the power supply decoupling
4, signal filtering and protection
5. Safety
Mobile radio emissions
Layout
stacked structure: strict control of characteristic impedance is within specifications, to ensure that the distance to the reference alignment layer is less than the distance to the other layer, which is a prerequisite board EMC design. Reference plane as complete as possible, preferably a high-speed reference signal GND.
http://www.eda365.com/forum-271-1.html
high-speed circuit low-speed circuit and a digital circuit and an analog circuit, the IO circuit, has its own area as much as possible, to avoid duplication.
Manner functional modules divided areas, to avoid overlap region,
Electronic circuit macro photographs. PCBs in lighting
Layout requirements:
1, the high frequency signal separated from the input and output signals.
2, clock chip / away from the opening of the MOS transistor IO connector.
3, the associated function module is placed close to the connector.
4, the wiring layer is smaller than the distance from the reference layer to the other layers of the distance.
5, the platen structure must ensure the characteristic impedances of the traces within specifications.
Wiring
a wiring guidelines, the current must form a complete loop, so we have to artificially set a path to let it follow the path we want to go, and let the loop area as small as possible.
The current path forward is that we actually Lay the line, then its return path reverse it.
Ground current of the high frequency signal will always choose the impedance Z (not resistance R) take the path of least, this path is not a straight path to the terminal (the minimum resistance R) of the source, but the trace path on a reference mirror layer (minimum impedance Z), which is adjacent walking path line projected on the reference plane. We have to do is to ensure that this path is continuous, constituting this loop area is minimal, electromagnetic radiation generated is minimal.
Loop signal to be truly continuous whole, not just the alignment section further includes a source terminal and a terminal, even taking into account the internal IC.
Signal reflux:
高速信号的回流电流并不是完全分别在信号线的正下方，而是按一定的电流密度分布在其正下方及两侧，其正下方的电流密度最大，往两侧递减，如果信号太靠近板边，就会有部分回流电流通过空间辐射的形式返回源端，这样就造成电磁辐射。
布线规则:
1,高速信号参考完整的参考面，不得有跨岛；
2,与其岛边（电源岛，地岛）间距至少3W；
3,对于分割了GND_Chassis的IO口，每个IO口都要有GND到GND_Chassis的电容。
那些情况会导致回路不连续：换层，跨岛，参考层不完整。
换层分几种情况：信号换层但参考面不变，参考面改变但其属性不变，参考面改变且其属性也改变。
跨岛：走线在参考面的投影区铜皮没有连续（示意图如下）。
布线规则：
在两个地层直接换层加地钉；
地钉或过孔电容与换层过孔间距最大不能超过3W；
换层过孔应在参考平面内，而不能在参考平面之外或边缘；
前提条件，面临过孔或跨岛的选择时，应选择过孔；
时钟信号不允许跨岛。
时钟信号、高速信号与其他信号线间距至少3W；
时钟信号，高速信号走线不得穿过高速、大功率等器件，以及不能穿过IO连接器和插槽下方；
时钟芯片，时钟Buffer等高速器件下方不能有其他信号穿过；
时钟信号力IO连接器侧板边300mil以上，在其他位置离板边200mil以上；
自身有绕线时（比如蛇形绕线），线间距至少5W；
走线不得与IO线并行走线，且线间距至少5W;
时钟线尽可能在内层走线；
差分对于差分对之间间距保证20mil以上；
按照信号流向走线，滤波器和变压器的初、次级信号走线不可重叠，蛇形绕线的走线也有此要求；
RGB型号与其他信号线和岛边（电源岛，地岛）间距至少5W;
IO电路从连接器往里看，要先进过防护器件，然后再是滤波电路，且都需要靠近连接器。
高速信号在经过滤波器件和防护器件的时候，要按照信号流向依次通过，不能出现分支走线，如 ，RGB信号要从防护IC的PIN脚上穿过，不能单独引分支线到防护IC上。
时钟信号线可以在参考平面进行切换，但切换次数需要尽量可能控制在3次以内；
时钟信号的源端匹配电阻要靠近时钟输出脚放置；
RGB信号的阻抗匹配，要按照芯片的设计指导设计；
走线拐弯使用钝角，不能使用直角和锐角；
高速信号和时钟信号不能出现没有端接的情况，特别是预留方案时，信号的两端都有预留有0欧姆电阻。
串扰：
信号走线间距如果太小，由于走线之间的分布电容影响，信号线之间的高频信号会相互串扰，影响信号质量，造成EMC问题。
特别是IO信号，如果串扰到了高频的噪声，就很容易通过外设引线造成严重的辐射。
信号线之间的分布电容与走线的间距，并行走线的长度，正对面积等因素有关，因此为了减少信号线之间的串扰，应该增大走线间距，减少并行走线的长度。相邻走线层要避免并行走线，因为其分布电容也很大，原则上要求垂直走线。
串扰的程度除了与分布电容有关外，还和信号的频率、幅度有关，这就是为什么高频信号更容易发生串扰。
阻抗匹配
对于高速信号来说，其走线路径都要求阻抗匹配，阻抗不匹配时会在阻抗不连续点产生反射，从而会影响信号质量，产生EMC问题。
如果一组信号从源端-走线-终端这样一个路径上，源端阻抗=走线的特性阻抗=终端阻抗，这种理想情况下就不会发生反射。可以这样理解，阻抗变化越大，信号反射就越大，产生的EMC问题也就越严重，分支走线，终端空载等情况都是很严重的阻抗不匹配。
电源去耦
功能模块之间（芯片之间），电源和地时共用的，模块工作时产生的噪声很容易通过这两个公共的路径相互耦合，造成严重的EMC问题。
地往往会做到很大的面积，而且是单独的一层，这样相对来说比较干净（噪声非常小）。
电源则需要去藕，保证电路工作时不对其他电路产生影响。
为了保证电容的滤波效果，电容到电源或地的阻抗Z必须尽量小。
对于走线的电源，保证每个电源PIN脚都有一个0.1uF的电容，走线要加粗。
对于BGA的芯片，则四个角上分布0.1uF，0.01uF的电容至少各一个。
电源的滤波电路参照原理图放置，电容和磁珠尽量靠近芯片放置。
滤波电容尽可能直接打孔到地层，如果必须使用走线时，走线要保证短而粗。
A power supply or to ground via a maximum of two capacitors used.
Signal filtering and protection
IO signals generally need to connect peripherals, the peripherals are generally rather long connection, if the high frequency noise with the IO signal (including power and ground), it is easy by peripheral connecting a greater radiation to space, thus, the IO filtered signals are required.
In order to avoid signal after being filtered secondary pollution in the inner panel, the filter circuit to be placed close to the port.
External devices can be easily introduced outside interference, even destructive interference, therefore, require the use of protective devices, and should be placed before the filter circuit to prevent destructive interference causes the filter circuit failure.
Safety
Safety: There are electrical separation between the line must be able to withstand a predetermined voltage without the occurrence of dielectric breakdown.
Setting rule: copper (via trace shape pad) belonging to different lines of the airgap to guarantee a certain distance, a predetermined withstand voltage.
The same layer: outer insulating medium is air, the breakdown voltage strength of 3KV / mm. Inner dielectric of FR4.
Different layers: an insulating medium is FR4, breakdown electric field strength of 15KV / mm. ! ! ! Note that consider non-uniform electric field distribution.