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The crystal oscillator has two more important parameters, frequency offset and temperature offset. The units are PPM. In layman's terms, the nominal frequency of the crystal oscillator is not always stable. In some environments, the crystal frequency will have an error. The greater the error, the circuit stability The worse, the circuit may not work properly.
Therefore, the layout of the crystal oscillator is particularly important when designing the PCB. The following points need to be paid attention to.
✔ Place the two matching capacitors as close as possible to the crystal oscillator.
匹配电容靠近晶振放置
✔ The crystal oscillator is made of quartz crystal, which is easily affected by external impact or drop. Therefore, it is best not to place it on the edge of the PCB and to place it as close to the chip as possible during layout.
✔ The trace of the crystal oscillator needs to be protected with GND and kept away from sensitive signals such as RF, CLK signals and high-speed signals.
✔ In some PCB designs of crystal oscillators, adjacent layers are hollowed out (clearance) or the same layer and adjacent layers are treated with clearance. The third layer needs to have a complete ground plane. The reason for this is to maintain a constant load capacitance.
The formula for calculating the load capacitance of the crystal oscillator is: CL=C1*C2/(C1+C2)+Cic+Cp
Cic is the internal capacitance of the integrated circuit, and Cp is the parasitic capacitance of the PCB board. If the parasitic capacitance is too large, the load capacitance will be too large, which will cause the crystal frequency deviation. At this time, reducing the matching capacitance C1 and C2 may improve it, but This is also a measure to treat the symptoms but not the root cause.
How to control the parasitic capacitance Cp when the adjacent layer of the crystal is hollowed out?
The physical formula of the capacitance is: C=εS/4πKd, that is, the area S and the distance d between the crystal pad and the adjacent ground plane will affect the size of the parasitic capacitance. Because the area S is constant, the only factors affecting the parasitic capacitance are With the remaining distance d, by hollowing out the ground of the same layer of the crystal oscillator and the ground of the adjacent layer, the distance between the crystal oscillator pad and the ground plane can be increased to achieve the effect of reducing parasitic capacitance.
电容容值和物理量之间的关系
A simple picture is drawn, the following is a 4-layer board, the crystal oscillator is placed on the top layer, after the top layer and adjacent layers are cleared, the crystal oscillator is relative to the ground plane (L3), and the distance d is increased compared to before there is no clear space , That is, the parasitic capacitance will be reduced.
晶振的L1和L2层均净空处理
✔ Place the crystal oscillator away from the heat source, because high temperature will also affect the frequency deviation of the crystal oscillator.
We know that the neighboring hollowing out treatment near the crystal oscillator is to maintain a constant load capacitance on the one hand, and a big reason is to isolate heat conduction, to prevent the heat of the surrounding PMIC or other heating elements from being conducted to the crystal oscillator through the copper skin, resulting in frequency On the contrary, deliberately, the clear space is not covered with copper to isolate the heat transfer.
Why does temperature affect the crystal frequency?
When the crystal is heated or lowered to a certain temperature and then lowered to room temperature, there will be a certain change from the initial test at room temperature. This is due to the thermal hysteresis of the crystal. The accuracy of the TCXO with temperature compensation is relatively better. , Can effectively solve the crystal temperature drift, but generally TCXO is more than M grades, few KHz, limited by the production process.
Today's article is over here. I hope it will be helpful to you. See you in the next issue.