Getting Started with Verilog (9) (Modeling Example)

Different ways of modeling

Use the data flow method, behavioral method and structural method to model the circuit shown in the figure below:

Data flow approach: modeling circuits using continuous assignment statements

module Save_Mult_Df(A, C, ClkB, Z);
  input[0:7] A;
  input[0:3] C;
  input ClkB;
  output[0:11] Z;
  wire S1;

  assign Z = S1 * C;
  assign S1 = ClkB ? A : S1;
endmodule

Behavior: Use the always statement with a sequential program block to model the circuit as a sequential program description.

module Save_Mult_Df(A, C, ClkB, Z);
  input[0:7] A;
  input[0:3] C;
  input ClkB;
  output[0:11] Z;
  reg[0:11] Z;

  always@(A or C or ClkB) begin:SEQ
    reg[0:7] S1;
    if(ClkB)
      S1 = A;
    Z = S1 * C;
  end
endmodule

Structure method: It is assumed that 8-bit registers and 8-bit multipliers already exist, and the circuit is modeled as a line netlist.

module Save_Mult_Df(A, C, ClkB, Z);
  input[0:7] A;
  input[0:3] C;
  input ClkB;
  output[0:11] Z;
  wire[0:7] S1, S3;
  wire[0:15] S2;

  Reg8 R1(.Din(A), .Clk(ClkB), .Dout(S1));
  Mult8 M1(.A(S1), .B({
    
    4'b0000, C}), .Z(Z));
endmodule

Conditional operation modeling

Operations that occur under specific conditions can use continuous assignment statements with conditional operators, or use statements within always statements or < /span> statement modeling. An arithmetic logic circuit is described below:ifcase

module Simple_ALU(A, B, C, PM, ALU);
  input[0:3] A, B, C;
  input PM;
  output[0:3] ALU;

  assign ALU = PM ? A + B : A - B;
endmodule

Multi-select switches can also be modeled using the always statement. First determine the value of the selected line, and then, the case statement selects the corresponding input and assigns it to the output based on this value.

`timescale 1ns/1ns
module Multiplexer(Sel, A, B, C, D, Mux_Out);
  input[0:1] Sel;
  input A, B, C, D;
  output Mux_Out;
  reg Mux_Out;
  reg Temp;
  parameter MUX_DELAY = 15;

  always@(Sel or A or B or C or D)
    begin:P1
      case(Sel)
        0: Temp = A;
        1: Temp = B;
        2: Temp = C;
        3: Temp = D;
      endcase
      Mux_Out = #MUX_DELAY Temp
    end
endmodule

general purpose shift register

The universal serial input, serial output shift register can be modeled using the loop statement within the always statement block. The number of registers is defined as a parameter so that the number of universal shift registers can be modified when referenced in other designs. for

module Shift_Reg(D, Clock, Z);
  input D, Clock;
  output Z;
  parameter NUM_REG = 6;
  reg[1:NUM_REG] Q;
  integer P;

  always@(negedge Clock) begin
    // 寄存器右移一位
    for(P=1; P<NUM_REG; P=P+1)
      Q[P+1] = Q[P]
    // 加载串行数据
    Q[1] = D;
  end

  // 从最右端寄存器获取输出；
  assign Z = Q[NUM_REG];
endmodule

State machine modeling

A state machine can typically be modeled using a statement followed by a always statement. Status information is stored in registers. Multiple branches of the statement contain behavior for each state. The following is an example representing a simple multiplication algorithm for a state machine:casecase

module Multiply(Mplr, Mcnd, Clock, Reset, Done, Acc);
  input[0:15] Mplr, Mcnd;
  input Clock, Reset;
  output Done;
  reg Done;
  output[31:0] Acc;
  reg[31:0] Acc;
  parameter INIT = 0, ADD = 1, SHIFT = 2;
  reg[0:1] Mpy_State;
  reg[31:0] Mcnd_Temp;

  initial Mpy_State = INIT;

  always@(negedge Clock) begin:PROCESS
    integer Count;
    case(Mpy_State)
      INIT:
        if(Reset)
          Mpy_State = INIT;
        else
          begin
            Acc = 0;
            Count = 0;
            Mpy_State = ADD;
            Done = 0;
            Mcnd_Temp[15:0] = Mcnd;
            Mcnd_Temp[31:16] = 1'd0;
          end
      ADD:
        begin
          if(Mplr[Count])
            Acc = Acc + Mcnd_Temp
            Mpy_State = SHIFT;
          end
      SHIFT:
        begin
          Mcnd_Temp = {
    
    Mcnd_Temp[30:0], 1'b0};
          Count = Count + 1;
          if(Count == 16)
            begin
              Mpy_State = INIT;
              Done = 1;
            end
          else
            Mpy_State = ADD;
        end
    endcase
  end
endmodule

Moore Finite State Machine Modeling

The output of a Moore finite state machine (FSM) depends only on the state and not on its input. The behavior of this type of finite state machine can be modeled by using statements with case statements that transition on state values. always

module Moore_FSM(A, Clock, Z);
  input A, Clock;
  output Z;
  reg Z;

  parameter STO = 0, ST1 = 1, ST2 = 2, ST3 = 3;
  reg[0:1] Moore_State;

  always@(negedge Clock)
    case(Moore_State)
      ST0: begin
        Z = 1;
        if(A)
          Moore_State = ST2;
      end

      ST1: begin
        Z = 0;
        if(A)
          Moore_State = ST3;
      end

      ST2: begin
        Z = 0;
        if(~A)
          Moore_State = ST1;
        else
          Moore_State = ST3;
      end

      ST3: begin
        Z = 1;
        if(A)
          Moore_State = ST0;
      end
    endcase
endmodule

Mealy type finite state machine modeling

In a Mealy-type finite state machine, the output depends not only on the state of the machine but also on its inputs.

module Mealy_FSM(A, Clock, Z);
  input A, Clock;
  output Z;
  reg Z;

  parameter STO = 0, ST1 = 1, ST2 = 2, ST3 = 3;
  reg[1:2] P_State, N_State;

  always@(negedge Clock)
    P_State = N_State;

  always@(P_State or A) begin:COMB_PART
    case(P_State)
      ST0:
        if(A) begin
          Z = 1;
          N_State = ST3;
        end
        else
          Z = 0;

      ST1:
        if(A) begin
          Z = 0;
          N_State = ST0;
        end
        else
          Z = 1;

      ST2:
        if(~A)
          Z = 0;
        else begin
          Z = 1;
          N_State = ST1;
        end

      ST3:
        begin
          Z = 0;
          if(~A)
            N_State = ST2;
          else
            N_State = ST1;
        end
    endcase
  end
endmodule