HDLBits-Verilog learning record | Getting Started

1.Getting Started

problem: Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).

The answer is not unique, just for reference:

module top_module( output one );

// Insert your code here
    assign one = 1;

endmodule

Related explanation:
top_moduleThe top-level module cannot be modified

2.Output Zero

problem: Build a circuit with no inputs and one output that outputs a constant 0The
answer is not unique, just a common reference:

module top_module(
    output zero
);// Module body starts after semicolon
	assign zero = 0;
endmodule

Related explanation: This is quite similar to the syntax style of C language