Microcomputer Principles and Interface Technology Intel8060 Microprocessor
This bolg mainly talks about the internal structure, pin functions and bus timing of the 8060 microprocessor
8086 internal structure:
8086CPU is composed of two parts: the execution instruction component EU and the bus interface component BIU.
1. EU unit (execution unit) : controls and executes instructions, mainly composed of arithmetic logic unit ALU, EU control unit, 8 16-bit registers and a flag status register FALAGS
2. BIU unit (bus interface unit): responsible for slave memory Prefetch instructions and data, as well as all bus operations required by EU to communicate between the CPU and memory and peripherals. BIU mainly consists of instruction queue, instruction pointer register, segment register, and address adder. The following is a picture of the combination
of EU and BIU:
The following is a picture of the EU components:
introduced from top to bottom: AX, BX, CX, and DX, the four 16 Bit registers can be split into two 8-bit registers. For example, AX can be split into AH and AL. AH is the upper 8 bits (H is the abbreviation of High), and AL is the lower 8 bits (L is the abbreviation of Low). ) Below are four 16-bit registers, SP, BP, DI, and SI. SP and BP are related to addresses. SP is used to indicate the stack. BP can access the stack. DI and SI can also store addresses. The point! ! ! : The registers that can store addresses are BX, BP, DI and SI. The other registers cannot store addresses.
ALU is an arithmetic logic component and is used for calculations.
FLAGS is a status flag register. After the ALU operation is completed, it does not care whether the result can be used. FLAGS can choose or reject the operation result.
The following is the composition diagram of the BIU component:
When the EU component is executing instructions, the BIU component will prefetch the instructions to be executed next and put them in the instruction queue buffer. After the instructions in the EU component are executed, they are directly The instruction is fetched from the instruction queue buffer and execution continues.
This CS, DS. . . area called segment register
The area with this Σ symbol is a 20-bit adder. Its job is to shift the contents of the segment register to the left by four bits (equivalent to multiplying by 16), add the offset address, and generate the physical address, which is then cached. operate
Internal registers of 8086:
(The situation is different for different CPUs.)
It will be easier to remember if you have a picture with an English name:
- General registers: 8: AX (accumulation register), BX (base address register), CX (count register), DX (data register), SP (stack pointer register), BP (base pointer register), SI (source variable register) address register), DI (destination index register)
- 2 control registers: IP instruction pointer register and FLAGS flag register
- 4 segment registers: CS code segment register, DS data segment register, ES additional segment register, SS stack segment register