Chapter 2 Microcomputer Principles and Architecture

Chapter two

80386 addressing system

• Case without pagination

  Calculation steps: first obtain the segment selector of the program, find the segment base address (32 bits) according to the content of the segment selector, and then obtain the offset address used by the current instruction.

  32-bit linear address = segment base address (32 bits) + intra-segment offset (16 bits) + logical offset (32 bits)

  In the absence of paging, a linear address is just a physical address.

  

  The upper 13 bits are the descriptor index, and three 0s are added at the end to indicate the offset of the segment descriptor relative to the base address (equivalent to the first thirteen bits multiplied by 8H and shifted to the left by three bits, and the last three bits are zeroed as a whole)

  Bit 2 is the reference descriptor table indicator bit

  • TI=0: Read descriptors from the global descriptor table GDT
  • TI=1: Read the descriptor from the local descriptor table LDT

  Bits 1 and 0 are the request privilege level RPL

• 例：The base address of LDT is 00120000H, the base address of GDT is 0010 0000H, CS=1007Hand find the address of the segment descriptor

  解： CS = 0001 0000 0000 0111B

  So there are TI=1, RPL=11B=3andOFFSET（偏移地址） = 0001 0000 0000 0000H = 1000H

  Then the address of the segment descriptor is0012 0000H + 1000H = 0012 1000H

• 例: The base address of LDT is 0060 2000H, the base address of GDT is 0050 1000H, CS=2006H, EIP=0200Hfind the linear address of the code segment in memory.

  解：The title EIPrefers to the offset address

  So first calculate the segment descriptor address, CS = 0010 0000 0000 0110Bie TI=1,RPL=10B=2

  also haveLD = 2000H + 0060 2000H = 0060 4000H

  so线性地址 = LD + EIP = 0200H + 0060 4000H = 0060 4200H

• There is a case of pagination

  Answer the specific process of logical address to physical address translation in 80386 processor system.

  1. The CPU first obtains the segment selector and the offset address within the segment from the memory access instruction

  2. Query the corresponding segment descriptor from the segment table (GDT or LDT) according to the segment selector

  3. Generate a 32-bit linear address (virtual address under the page mechanism) based on the segment base address in the segment descriptor and the segment offset address in the instruction

  4. The 32-bit linear address is divided into three parts according to the design of the 80386 secondary page table: the upper 10 bits are used as the page directory entry index, the second highest 10 bits in the middle are used as the page table entry index, and the lower 12 bits are used as the page offset address.

  5. Obtain the physical page address of the second-level page table from the first-level page directory table through the high 10-bit page directory entry index (obtainable through the physical page frame number), and then find the corresponding page table entry index according to the middle 10-bit page table entry index. Physical page frame. According to the physical page frame number and the offset address in the page, the final physical address is jointly generated to access the physical memory.

Improvements in Microprocessor Architecture

• Layering of Storage Subsystems

  The key issue is: to build a storage system that meets the requirements of capacity and speed at a reasonable price, it is fundamentally necessary to coordinate the contradiction between speed, capacity and cost

• Secondary structure: memory (to solve the read and write speed) + external memory (to solve the storage capacity)

• Four-level structure: register + Cache + main memory (byte addressing) + auxiliary storage

  Cache-main memory structure solves the contradiction between high speed and low cost

  Main memory-auxiliary memory structure uses virtual memory to solve the contradiction between large capacity and low cost

• Pipeline: It divides the computer instruction processing process into multiple steps, and executes instructions in parallel through multiple hardware processing units to speed up instruction execution.

• Superscalar: A CPU with a superscalar architecture can simultaneously dispatch multiple instructions to be executed in different execution units in one clock cycle, which realizes the parallelism of the instruction set.

• Pipeline problems: Only when fully loaded can the best efficiency be exerted; the number of pipeline stages cannot be increased indefinitely; hardware costs will be increased; delays and additional overhead will be introduced, limiting the depth of the pipeline; Pipeline interrupted.

addressing mode

1. Immediate addressing: Operands are part of the instruction

   MOV AX,1234H
   ;小端序：高位：12->AH 低位：34->AL
   

2. Direct addressing: The operand required by the instruction is stored in the memory, and the effective address of the operand is directly given in the instruction.

   MOV AX,[1234H]
   ;MOV 不能直接进行两地址之间的内存交换
   

3. Register addressing: the operand is stored in the register, and the data is obtained by specifying the register

   MOV AX,BX
   

4. Register indirect addressing: the effective address of the operand is only in one of the four registers SI, DI, BX,BP

   MOV AX,[DI]
   ;[]取内存单元
   

5. Register-relative addressing: The effective address of the operand is the sum of the value of a base register ( BX, BP) or index register ( SI, DI) plus the 8-bit or 16-bit offset given in the instruction

   MOV AX, [BX + 1234H] ;或者 MOV 1234H[BX]
   

6. Base indexed addressing: The effective address of the operand is obtained by adding the value of one of the base registers ( BX, BP) to the value of one of the index registers ( SI, )DI

   MOV AX, [BX + DI]
   ;MOV AX, [BX][SI]
   

7. Base-relative indexed addressing: Adds an offset compared to base-indexed addressing

   MOV AX, 1234H[BX + DI]
   

exercise

• The 8086CPU divides the 1MB space into several logical segments, and each segment can contain up to 64KB storage units.

• The maximum addressable I/O space of 8086CPU is 64KB

• The internal memory address space in the 8086 system is 1M, and when performing I/O reading and writing, the effective address line is the lower 16 bits .

• If the main frequency of 8086CPU is 8MHz, its basic bus cycle is 500ns

• The virtual byte address 7FFFH-8000H may not be continuous in the physical address space

• ? 8086 has 2 CPU hardware interrupt pins , INTR/NMI is maskable interrupt signal and non-maskable interrupt signal INTA is interrupt response

• The 8086 CPU reads/writes the memory, and the operation that requires two bus cycles is to read/write a word from an odd address (16-bit data line, reading from an odd address is not the way to do it)

• In the segmentation and paging management methods of computer memory, segments can overlap, and pages cannot overlap

• The instruction queue class in the 8086 CPU can store 6 bytes of instruction codes

• In the storage paging management method, the purpose of constructing a multi-level page table is to reduce the number of page table entries

  Using multi-level page tables can save page table memory. Using a first-level page table requires continuous memory space to store all page table entries. Multi-level page tables reduce memory usage by requesting page tables only for those memory regions of virtual addresses actually used by the process

• Both 8086 and 80386 have instruction stream queues inside

• In protected mode, the segment register of the Pentium processor is used to select the segment descriptor

• When the 8086 pin signal M/IO=1, RD=0, WR=1, the operation completed by the CPU is memory reading (reading and writing are active at low level, M means memory)

• In the 8086 system, one bus cycle completes one memory read and write

• Four-stage pipeline CPU operation: fetch, decode, execute, write back

• The 16-bit processor 8086 reads and writes a continuous double-byte data, and the number of bus cycles may be one or two (when aligned, one cycle; when not aligned, two cycles)

• When the CPU calls a subroutine, the return address is pushed onto the stack

• The processors of Intel X86 and AMD have instruction set compatibility, and the instruction set is the same set.

• Programs designed for the X86 protection mode cannot run in the 8086 because the addressing modes are not compatible

• The essential difference between the real mode and the protection mode of Intel processors is the different task management mechanisms

• When the CPU calls a subroutine, the return address is pushed onto the stack

• The processors of Intel X86 and AMD have instruction set compatibility, and the instruction set is the same set.

• Programs designed for the X86 protection mode cannot run in the 8086 because the addressing modes are not compatible

• The essential difference between the real mode and the protection mode of Intel processors is the different task management mechanisms