[Notes] Microcomputer Principle and Interface Technology 2 -- Memory and IO Interface Technology

memory

Memory classification

Classification by material: semiconductor memory, magnetic memory, optical disk memory

Read-only memory (readonly memory, ROM): The stored content is fixed, that is, it can only be read and cannot be written
Random access memory (random access memory, RAM): The memory that can be read and written is called random access memory

Classified by function

• Main memory: Inside the host, it is used to store currently running programs and data
• Secondary Storage: Computer Peripherals
• Cache memory cache: very expensive, high speed, small capacity

Memory Common Performance Indicators

1. Throughput (throughput): the amount of data processed per unit time, commonly expressed in MB/s or IOPS (IO operations per second).
2. Bandwidth (bandwidth): The maximum data transfer rate that the memory can support, measured in bps (bits per second).
3. Latency: The time interval of data access, mainly refers to how long it takes to read or write data. The unit is usually milliseconds (ms). Low latency means higher performance.
4. I/O Operations Per Second (IOPS): The number of input/output (read/write) operations performed per unit time.
5. Random read/write ratio (random read/write ratio): Whether the memory supports random read and write, and how the random read and write performance is.
6. Available capacity: The actual capacity available in the storage, after formatting, RAID copy data and other factors need to be considered.
7. Capacity scalability (scalability): how much capacity the memory can be expanded to.
8. Disk Life Time (MTBF): Mean time between failures, a measure of storage reliability.

semiconductor memory

The figure above shows the architecture of a semiconductor memory

Address decoder: Receive the address signal sent by the CPU, and then generate an address decoding signal to select a certain storage unit in the storage matrix

Storage Matrix: A collection of basic storage units capable of storing binary information

Data input/output control circuit: mostly a three-state bidirectional buffer structure, so that the data input/output terminals of each memory chip in the system can be easily connected to the system data bus

random access memory RAM

In larger-capacity memories, the same bits of each word are often organized in one slice; these words of the same bit are usually arranged in the form of a matrix, such as 32×32=1024 or 64×64=4096. Then, the desired unit is selected by overlapping the X selection line (row line) and the Y selection line (column line)

The storage capacity is small, and the cell array of the RAM chip can also be directly arranged in the form of the required number of bits

The internal data of the memory is connected to the data bus through the I/O circuit and the input and output tri-state gates

The connection between RAM and CPU mainly has the following three parts

1. Address line connection
2. data link
3. control line link

DRAM

行地址选通信号(Row Address Strobe,RAS)和列地址选通信号(Column Address Strobe,CAS)Corresponding role:

• The RAS signal controls the writing of the row address, which is used to select the row in DRAM.
• The CAS signal controls the writing of the column address, which is used to select the column in the DRAM.
• During the writing of the row address, the column address remains unchanged; during the writing of the column address, the row address remains unchanged.
• The timing relationship of RAS and CAS signals is strict, which determines the speed and performance of DRAM.
• Generally, the RAS signal must be pulled down first and then the CAS signal must be pulled down.

Accordingly, it can be analyzed that DRAMthe operation is divided into the following steps:

1. Input a row address to the row address line, pull down the RAS signal to enter the row address write mode.
2. After waiting for the specified timing, input a column address to the column address line, pull down the CAS signal to enter the column address write mode.
3. After waiting for the specified timing, decide whether to perform a read operation or a write operation according to the read/write control signal.
4. After the operation is completed, set the RAS and CAS signals high to exit the current operating mode.

地址锁存器(Address Latch)It is a very important component in the computer system. Used to capture and save address information for subsequent processing, this is the main function:

1. Receive and store address information. The addresses held in the address latches can come from the CPU or peripherals.
2. Keep the address stable. Memory access usually includes an address phase and a data phase, and there is an interval between these two phases. The address latch can keep the address information unchanged during the data phase.
3. Provide subsequent modules to use. The address latch outputs the stored address for subsequent calculation or access.
4. Controls address latch timing. It controls when to latch the address through the trigger signal, and cooperates with the subsequent modules.

Typically, address latches are used for address access to memory or peripherals. The main working process is:

1. Receives an address information input.
2. The address is latched according to the trigger signal, and the address is saved.
3. The address of the output latch is provided for subsequent modules. such as memory or peripherals for access.
4. Keep the address output until the new address input to achieve the number of data accesses.

读周期specific steps

1. Address stage: CPU outputs memory address
2. Memory Latency: Memory Chips Retrieve Data
3. Data validity period: the memory returns data to the data bus
4. CPU read data: CPU gets data from the data bus
5. CPU usage data: CPU usage read data

tri-state buffer

三态缓冲器(Tri-State Buffer)A circuit component primarily used to control signals on a data bus.

A tri-state buffer has three possible output states:

• High level: output is logic 1.
• Low: Output is logic 0.
• High-impedance state: output tri-state (high impedance), disconnected from the data bus.

By controlling an enable signal, the tri-state buffer can select its output state.

The main features are:
when the enable signal is valid, the tri-state buffer works in the normal working mode (output 0/1).
When the enable signal fails, the tri-state buffer enters a high-impedance state and is disconnected from the data bus.
At this time other drivers on the data bus can control the output signal.

The main application of the tri-state buffer is:
shared data bus.
Interrupt data flow.
reduce bus current.

ROM

ROM can be mainly divided into the following categories

PROM(可编程只读存储器)

• Programming through physical holes, one-time programming. Once programmed, the content cannot be modified.
• The storage information will be burned in it, and then prop hole to lock the storage bit
• Low cost, fast speed, long storage time

EPROM(光可擦可编只读存储器)

• Can be programmed and erased multiple times using electronic methods.
• Use UV light to erase the circuit, then use a programmer to reprogram
• Only the entire EPROM chip content can be erased at one time

EEPROM(电可擦可编只读存储器)

• Can be electronically programmed and erased multiple times without the need for UV light.
• Each memory cell (byte) can be programmed and erased individually.
• High cost and slow

FLASH ROM

• Similar to EEPROM, but programmed and erased through the entire block, faster than EEPROM.
• Erasing by releasing electrons
• At least 64KB of data can be erased each time, and the maximum can be the entire chip
• Cost between EPROM and EEPROM

Memory and CPU link

片选
Select the corresponding chip through high and low levels, generally there are two level selection methods:
High level chip selection: When the chip selection pin is pulled high, the corresponding chip is activated and can work. If it is pulled low, it will be prohibited from working.
Low level chip selection: the other way around

Chip selection usage scenarios

• When the CPU accesses the memory, the chip selection of the corresponding memory chip is generated through the address decoder.
• When the chipset accesses the PCI device, it needs to generate different chip selection signals for different devices.
• When multiple memory channels are formed, different chip selects are generated for the memory of different channels.

地址译码器
Because the address issued by the CPU is usually encoded in binary, and a unique wiring method is usually used inside the memory chip to identify the address. At this time, the decoder is needed to realize the conversion of the address

Generally, address decoders have the following types: gate circuit decoder, 1-in-N decoder and PLD (programmablelogicdevice, programmable logic device) decoder

74LS138 is a commonly used 1-of-8 decoder, which inputs 3-bit binary code and generates a low-level chip select signal at 8 output terminals, so it is also called a 3-8 decoder

storage space expansion method

Bit extension, word extension, and word bit extension are three methods of data extension in computer architecture.

Bit extension refers to extending the data width by adding extra 0 bits to the data. For example:

• 4-bit data 0011is bit-extended to 8-bit as00110000
• The data width nis extended from bit to n+mbit, with mbit 0 extended.

Word expansion refers to extending the word length by using the same data to form multiple identical words. For example:

• 4 bits 0011are extended to 8 bits by 2 times word as00111100
• The data width nis expanded from bit to 2*nbit , and the same data is repeated.

The word bit expansion is to expand the word first, and then combine the high and low bits. For example:

• 4 bits 0011are obtained by double word expansion first 00111100, and then the high and low bits are combined into0011111100
• The data width is nextended from to 2*n + nbits .

The characteristics of these three extension methods:

• Bit extension: add 0, the simplest but inefficient.

• Word expansion: Duplicate data, often used to expand a small amount of data.

• Word bit expansion: make full use of data, and the expansion efficiency is high.

Memory addressing method (chip selection method)

There are three common methods of memory addressing:

Line Select:

• Access to the corresponding memory line is realized by activating the corresponding line selection.
• For example, 8 memory lines need 3 address lines AAA, 000~111 respectively select 0~7 lines.
• Simple and practical but the addressable number is limited, only 2^n lines can be accessed.

Full Decode (Full Decode):

• Completely decode the address and drive the corresponding memory chip select line.
• For example, a 10-bit address requires 10 chip select lines, and 2^10=1024 storage units can be accessed.
• The addressable quantity is large, but the cost is high, and it takes up many lines.

Partial decoding method (Partial Decode):

• Decode the high address bit part, and use the line selection method for the low address bit.
• For example, the upper 6-bit decoding drives 64 chip select lines, and the lower 4 bits select one of them through line selection.
• 2^10 units can be addressed, but only 64 chip select lines are required.
• Find a balance between addressability and complexity.

Comparison of the three methods:

• The line selection method is low in cost but has a limited number of addresses.
• The full decoding method can address a large number, but the cost is high, and it takes up a lot of lines.
• The partial decoding method strikes a balance between addressable quantity and complexity.

Memory subsection thought questions

Why does dynamic RAM need to be refreshed regularly?

Dynamic RAM (DRAM) needs to be refreshed periodically because its memory cells use a capacitor to hold charge information.

The storage unit is composed of a thyristor and a capacitor, and the presence or absence of charge represents the stored 0 and 1. But the capacitor will slowly leak charge over time, and the information will be lost.

To keep the charge from disappearing, DRAM needs to recharge its capacitors periodically, a process called "refreshing" or "refreshing".

The most fundamental factor in a CPU's ability to address memory depends on what

Address bus, data bus width, bus (Front side bus) frequency, instruction set support

I/O interface technology

Overview of the IO interface

As the name implies, the main functions of the available interface are as follows

(1) Data buffering: realize the speed matching between high-speed CPU and slow-speed external equipment.
(2) Signal conversion: Realize digital and analog conversion, serial and parallel format conversion, and level conversion
(3) Interrupt control: Realize CPU and external equipment parallel work and automatic fault handling, etc.
(4) Timing counting: Realize system timing and external event counting and control.
(5) DAM transmission: realize the direct exchange of information between the memory and the I/O device.

This is a typical IO interface circuit structure diagram

数据寄存器It is readable and writable, and is used to store information exchanged between the CPU and I/O devices.
控制寄存器It is used to store control commands and working mode settings sent by the CPU to external devices.
状态寄存器It is used to store the current working status information of the external equipment for query by the CPU.
数据缓冲器It is the channel for information transmission between CPU and I/O equipment. It is connected with the data bus DB of CPU. The information exchanged between I/O equipment and CPU is carried out through the data buffer.

IO port addressing addressing

When the CPU communicates with peripherals, it needs to transmit many different information. These registers and their control logic are collectively referred to as I/O ports (port)

数据端口
Store the data sent by the peripheral to the CPU and the data to be output by the CPU to the peripheral. These data are the most basic information exchanged between the host and the peripheral

状态端口
Mainly used to indicate the current status of peripherals. In addition to the content in the status port, there are often several status lines in the interface circuit, which use the level of the level to indicate the current status of the peripheral

命令端口（控制端口）
Store various commands and control words sent by the CPU to the interface in order to control the actions of the interface or equipment (common command information bits include start bit, stop bit, and enable interrupt bit)

There are two addressing methods for I/O ports, which are called memory-mapped addressing and I/O individual addressing.

存储器映象寻址方式
If each I/O port in the system is regarded as a storage unit and uniformly addressed as the storage unit, all instructions for accessing the memory can be used to access the I/O port without setting special I/O instructions

I/O单独编址方式
Individually address the I/O port addresses in the system to form an I/O space. They do not occupy storage space, but use special IN instructions and OUT instructions to access such ports with independent address spaces.

Input and output control method

These four are common I/O control methods in program design and system structure:

Program controlled mode (Program controlled I/O):

• Divided into two ways of unconditional transmission and conditional transmission
• Unconditional transmission: when the peripheral is ready, there is no need to query the status of the peripheral for information transmission
• Conditional transmission: The CPU continuously reads and tests the status of the external device by executing the program. If the input external device is in the ready state or the output external device is in the idle state, the CPU executes the information instruction

Interrupt Control Mode (Interrupt controlled I/O):

• Trigger an interrupt when the I/O is complete, and jump to the interrupt service routine.
• Make the CPU process when I/O is ready, which is more efficient.
• Interrupts are inserted between programs, and overclocking information needs to be saved. There is a certain cost.

Direct Memory Access (DMA):
When an external device needs to input/output a batch of data, it sends a request to the DMA controller. After receiving the request, the DMA controller sends a bus request to the CPU. If the CPU responds to the request of the DMA and assigns the right to use the bus to the DMA controller, the data can be directly processed by the DMA controller without passing through the CPU. After the batch of data transfer is completed, the DMA controller sends an "end interrupt request" to the CPU, and the CPU responds to the interrupt request to take back the right to use the bus.

I/O processor control mode:

• Interaction with peripheral devices is handled using a dedicated I/O processor.
• The I/O processor is independent of the CPU and focuses on I/O operations.
• The CPU only needs to communicate with the I/O processor to indirectly realize the interaction with the peripherals.
• The I/O processor has high efficiency and can effectively reduce the pressure on the CPU.

Four efficiency:
program control method < interrupt control method < DMA < I/O processor

Parallel Channels and Parallel Interfaces

This is a simple diagram of the 8255A structure

8255A is a parallel input/output interface chip that can provide three 8-bit channels.
Each port can be configured as input or output mode by programming its internal registers.
Mainly configure the port mode and direction through the control word register, then read the input port through the input status register, or control the output port through the output control register

Serial Communication and Serial Interface

The role of the modem is to encode and decode data, making it more suitable for high-speed transmission of large data

There are three types of signal modulation

1. Frequency modulation, using frequency shift keying method FSK (frequencyshiftkeying)
2. AM, using amplitude shift keying ASK (amplitude shiftkeying)
3. Phase modulation, using phase shift keying method PSK (phaseshiftkeying)

Synchronous and asynchronous communication

同步通信
It means that at the agreed communication rate, the clock signal frequency and phase of the sending end and the receiving end are always consistent (synchronous)

• The sending end and the receiving end use the same clock, and work synchronously based on the clock, so the clock signal is also transmitted while transmitting data
• A continuous stream of character bits is always maintained on the transmission line. If the computer is not transmitting, the line is filled with special "idle" or sync characters.
• The sending end will only send data on the rising or falling edge of the clock, and the receiving end will only receive data on the corresponding edge of the clock
• There is no handshake signal between sending and receiving, it is completely time-dependent and coordinated based on clock cycles

The following are the data segment formats corresponding to several common synchronization forms

异步通信
The time interval between two characters in communication is not fixed, but the time interval between each bit in a character is fixed

• The specified character is composed of start bit (startbit), data bit (databits), parity bit (parity) and stop bit (stopbits)
• When a character is transmitted, it starts with a low-level start bit, followed by data bits; the last transmission is a high-level stop bit; the idle bit between the end of the stop bit and the start bit of the next character To be filled by a high level "1"
• The sending end informs the receiving end that the data is valid through a manual signal (such as a handshake line), and the receiving end captures the data based on the signal
• The interval between sending data and receiving data can be any clock, completely independent of the clock