foreword
A summary of some conceptual basic knowledge for the end-of-term review of microcomputer principles.
content
(1) What are the similarities and differences among microprocessors, microcomputers, and microcomputer systems?
(1) The CPU (computing unit and controller) is built on a chip using large-scale integrated circuit technology, which is a microprocessor .
(2) A microprocessor plus a certain amount of memory and external devices (or external device interfaces) constitutes a microcomputer (that is, a microcomputer) . (3) The microcomputer system
is formed by combining the microcomputer with the software for managing and maintaining computer hardware and supporting applications .
(2) Briefly describe the hardware composition and functions of each part of the microcomputer system
(1) Arithmetic unit (ALU): The core of the arithmetic unit is the arithmetic logic unit, which is a component that completes various arithmetic and bare-metal operations.
(2) Controller (CU): A component that sends out various control information to coordinate the work of various components of the computer.
(3) Memory (M): A component that stores programs and data.
(4) Input device (IN): A component that inputs programs and data.
(5) Output device (OUT): A component that outputs result data and other information.
(3) What is the basic concept of microcomputer bus? What are the types of microcomputer bus? What are the characteristics of the bus structure?
(1) Concept: The so-called bus is the common line that connects components and transmits information.
(2) Type: address bus, data bus, control bus.
(3) Features: simple structure, high reliability, easy design, production and maintenance, and more importantly, easy expansion.
(4) What are the number systems of computers? How to convert the number system? Convert a decimal number to binary and hexadecimal: 128
(1) Number system: binary, octal, decimal, hexadecimal.
(2) Number system conversion: By continuously dividing by the target system, the remainder and the quotient are obtained until the quotient is 0. Arrange the remainder from bottom to top to get the target value.
(3)
Binary of <1>128:
,<2>128 hexadecimal:
(5) What parts does the CPU consist of in its internal structure?
The internal structure of the CPU is composed of various parts such as an arithmetic unit, a controller, a register array, and an internal bus.
(6) What are the functions of the bus interface components of the CPU? What are the functions of the execution unit of the CPU?
(1) Interface components: Responsible for data transmission between the CPU and memory, input and output devices.
(2) Execution unit: Responsible for executing the instruction set of the CPU.
What are the registers in 8086/8088 microprocessor? Which of the general-purpose registers can be used as address pointers?
8 general-purpose registers: AX, BX, CX, DX, SP, BP, SI, DI.
2 pointer registers: SP, BP.
4 segment address registers: DS, ES, SS, CS.
(7) Briefly describe the meaning and function of each bit of the 8086CPU flag register
- CF (Carry Flag): Carry flag, used to indicate whether carry or borrow occurs in unsigned arithmetic operations.
- PF (Parity Flag): Parity flag bit, used to indicate whether the number of 1s in the operation result is odd or even.
- AF (Auxiliary Carry Flag): Auxiliary carry flag bit, used to indicate the low to high carry in BCD (binary coded decimal) arithmetic operation.
- ZF (Zero Flag): Zero flag, used to indicate whether the operation result is zero.
- SF (Sign Flag): Sign flag bit, which is used to indicate the sign of the operation result. If the result is negative, SF is set to 1, otherwise it is set to 0.
- TF (Trap Flag): Trap flag bit, used for debugging purposes, when set to 1, the CPU generates an interrupt after each instruction is executed.
- IF (Interrupt Flag): The interrupt flag bit is used to control the CPU's response to maskable interrupts. When set to 1, it allows the response to maskable interrupts.
- DF (Direction Flag): The direction flag bit is used to control the direction of the string operation. When it is set to 1, the string operation is performed from the high address to the low address, otherwise it is 0.
- OF (Overflow Flag): The overflow flag bit is used to indicate whether the signed arithmetic operation overflows.
(8) Various addressing modes of 8086, and write 2 or 3 transfer instructions for each addressing mode.
(1) Immediate addressing
MOV AX, 1234h
MOV BX, 2244h
(2) Register addressing
MOV AX, BX
MOV BX, AX
(3) Register indirect addressing
MOV AX, [BX]
MOV BX, [AX]
(4) Register relative addressing
MOV AX, [BX+3]
MOV AX, 3[BX]
(5) Direct addressing
MOV AX, [1234h]
MOV BX, [1234h]
(6) Base address indexed addressing
MOV AX, [1234h]
MOV BX, [1234h]
(7) Base-indexed relative addressing
MOV AX, [BX+SI+4]
MOV BX, [BP+DI+4]
(9) PCI bus characteristics
(1) Outstanding high performance, realize the synchronous operation of 33MHZ and 66MHZ, the transmission speed can reach 528Mb/s, and support burst transmission.
(2) Good software and hardware compatibility, supporting various processors.
(3) Support plug and play, support multi-master devices.
(4) Provide data and address parity check function to ensure data integrity.
(5) Optimal chips and multiplexed signal lines are used, and the cost is low.
(10) Briefly describe the relationship between the AGP bus and the PCI bus
(1) The AGP standard is fully compatible with the PCI standard, and an AGP device can exchange data with memory through both the AGP standard and the PCI standard.
(2) AGP is an expansion and enhancement of PCI.
(3) AGP is not an upgraded version of PCI, its slot is not compatible with PCI.
(11) Briefly describe the characteristics and applications of the USB bus
Features:
(1) With plug and play feature.
(2) Peripherals can be dynamically linked and reconfigured.
(3) Allow multiple devices to work at the same time.
(4) Can supply power to devices on the USB bus.
(5) The communication protocol supports a mixed mode of isochronous data transmission and asynchronous message transmission.
(6) Support real-time voice, audio, and video data transmission.
Applications:
(1) Computer peripherals
(2) Mobile device connectivity
(3) Storage devices
(4) Digital cameras and camcorders
(5) Video and audio equipment
(6) Game controllers
(7) Embedded systems
(12) What types of data information are there? What types of information are sent between the CPU and the I/O devices? What is the corresponding port?
(1) Digital quantity, analog quantity and switch quantity.
(2) Data information, status information and control information.
(3) Data port, status port and control port.
(13) What types of data information are there? What types of information are sent between the CPU and the I/O devices? What is the corresponding port?
(1) There are three types of digital information: digital quantity, analog quantity and switch quantity.
(2) Data information, status information and control information.
(3) Data port, status port and control port.
(14) What is an IO interface? What are the basic functions and functions of the IO interface?
(1) IO is a standardized logical component connected between the CPU, main memory and peripheral devices through the system bus.
(2) The IO interface acts as a "connector" between two components in order to realize information transmission between each other.
(15) Which two methods are usually used by the computer to address the IO port? Which method is used in the 8086 microcomputer system?
(1) I/O ports and memory are uniformly addressed; I/O ports are individually addressed.
(2) The 8086 system uses a separate addressing method for I/O ports.
(16) What is the IO port address range of 8086CPU? What is the IO port address range in IMB PC? Which address ranges are available to users?
（1）0-0xfffff。
（2）0-0xfffff。
（3）0-0xffff。
(17) Set the IO port address of a peripheral interface to 208H, and design a port decoder for this interface.
(1) Recommended video explanation: https://www.bilibili.com/video/BV1yP411N7A6/?spm_id_from=333.337.search-card.all.click&vd_source=a6289e7ab435b598d918e64d45cd15c0 (
2) It is very simple to memorize routines for this kind of topic
<1> First of all, we need to know what the IO port address of the peripheral interface represents. Take 208H here as an example, 208H=10 0000 1000B, then it means that if A9 and A3 are at high level, other pins and AEN pin are at low level Then select the current IO for a long time. (When AEN is low, it means I/O access controlled by the CPU, so to select IO, AEN must be low)
<2> Now we know what the voltage of these 11 lines should be, and there are It is required that this IO must be selected at this level. Then we can use NAND gates and NOR gates . The NAND gate stipulates that 0 is 1, and the NOR gate is 1 and 0.Using this feature, when the address line needs to be 0, put a NOR gate, and if the address line is 1, directly connect the NAND gate.
<3>Taking this topic as an example, because A9 and A3 are high level, they are directly connected to the NAND gate. While the other address lines are all low level, then a NOR gate is interspersed between the address line and the NAND gate.
(18) Set the IO port address of a peripheral interface as 300H~307H, that is, the peripheral requires 8 consecutive IO port addresses, and design a port address decoder for this interface.
(1) This kind of question is an upgraded version of the previous question, and a 74LS138 chip needs to be added.
(2)
<1> First, we need to know which address lines 300H~307H have not changed. Obviously, only the three address lines A0 ~ A3 have changed, and the others have not changed.
<2> Therefore, we first connect AEN to E2. A0 ~ A3 are directly connected to the three pins of ABC.
<3> The other wires are the same as the previous question. The high level is directly connected to the NAND gate, and the low level is first connected to the NOR gate and then connected to the NAND gate.
(19) What are the data transmission methods between the CPU and peripherals? What are the characteristics of each transmission method and which applications are they suitable for?
(1) Data transfer method between CPU and peripherals:
<1> Unconditional transfer
<2> Query transfer
<3> Interrupt control
<4> DMA control method
(2)
<1> Unconditional transfer method is the simplest The program controls the delivery method. The program control input/output method refers to a method in which I/O instructions are used to perform input/output in the programming of the program.
<2> When querying the transmission mode, the CPU actively reads the status register through the program to understand the interface situation, and completes the corresponding data operation. Query operations need to be repeated at intervals of fewer clock cycles and are therefore CPU inefficient.
<3> In the interrupt transmission mode, when the program is running normally, if an external event with higher priority occurs, the CPU will be notified through the interrupt request, and the CPU will read the status register to determine the type of event, so as to execute different branch processing. This method has high CPU efficiency and good real-time performance.
<4> DMA (Direct Memory Access) transmission method, that is, direct memory access method. The specific process of data transfer is directly completed by the hardware (DMA controller) between the memory and IO, and the CPU only temporarily hands over the control right to the DMA at the beginning until the end of the data transfer. This method is faster than passing through the CPU, especially when transferring in batches.
(20) What is parallel communication? What are the characteristics of parallel communication?
(1) Parallel data communication refers to the data transmission method in units of bytes or words.
(2)
<1> The number of data bits transmitted each time is large and the speed is fast;
<2> The overhead of the signal transmission line is large (the number of data lines corresponds to the number of data bits transmitted), and the cost is high;
<3> Often used in short distances , High-speed data transmission occasions.
(21) When the data is read into the CPU from the port C of the 8255A to the data bus, what are the levels of the 8255A pins CS#, A1, A0, RD#, and WR#?
CS# should be low level to select the chip.
Only when A1 and A0 are 10 can the C port be selected.
RD# should be low level (negative pulse).
Read data into CPU, WR# is high level.
(22) Set the 4 port addresses of 8255A to 60H~63H, and try to write the initialization program in the following situations.
(1) Set group A and group B as mode 0, port A and port B are input, and port C is output.
<1> This kind of topic is actually relatively simple, just follow the routine.
<2> First of all, the title generally gives 4 port addresses, so we only need to look at the port address with the largest value. Because the default order of the 4 port addresses of 8255A is A, B, C, and control port. Because we are the initialization program here, we only need to pay attention to the control port.
<3> About the register introduction of the control port, we only need to know the following figure. (Generally speaking, the title will be given. There should not be 250 for you to remember)
<4> After knowing the process of the second and third steps. Now we can start to analyze how to do this problem. First of all, we know that the port with the largest number is 63H, so remember this number. Secondly, according to the requirements of the topic, port A is mode 0, input, so D6 and D5 are 00, and D4 is 0. Port B is mode 0, input, so D2 is 0 and D1 is 0. Port C is output, so D3 and D0 are 0. D7 defaults to 1.
MOV DX,0063H ;H表示16进制
MOV AL,10010010B ;B表示2进制
OUT DX,AL ;将数据写入地址63H
(2) Set group A as mode 2, group B as mode 1, and port B as output.
<1> Still according to the above figure, because A should be mode 2, so D6 is 1, and D5 is 0.
<2> Since group B is mode 1, D2 is 1. Group B is output, so D1 is 0.
<3> Except D7 is 1 by default, other bits can be written freely. For convenience, I set the other bits to 0.
MOV DX,0063H ;H表示16进制
MOV AL,11000100B ;B表示2进制
OUT DX,AL ;将数据写入地址63H
(3) Set both port A and port B to mode 1, both are input, and PC6 and PC1 are output.
<1>Because port A is mode 1, input. So D6 is 0, D5 is 1, and D4 is 1.
<2>Because port B is mode 1, input. So D2 is 1 and D1 is 1.
<3> Because PC6 and PC1 are output, D3 is 0 and D0 is 0.
MOV DX,0063H ;H表示16进制
MOV AL,10110110B ;B表示2进制
OUT DX,AL ;将数据写入地址63H
(4) Port A works in mode 1, input; port B works in mode 0, output; the high 4 bits of port C cooperate with port A, and the low 4 bits are input.
<1>Because port A is mode 1, input. So D6 is 0, D5 is 1, and D4 is 1.
<2>Because port B is mode 0, output. So D2 is 0 and D1 is 0.
<3>Because the upper 4 bits of C port work with A port, and A port is an input, so the upper 4 bits of C port PC4-PC7 should be output, and D3 is 0.
<4>Because the lower 4 bits of port C are input, D0 is 1.
MOV DX,0063H ;H表示16进制
MOV AL,10110001B ;B表示2进制
OUT DX,AL ;将数据写入地址63H
(23) How many channels does the programmable timer/counter 8253 have? How many working modes are there for each channel? What are the main characteristics of the various ways of working?
(1) 0, 1, 2 three channels.
(2) Each channel has 6 working modes.
(3)
<1> Mode 0: Interrupt generated when counting ends
<2> Mode 1: Programmable single-shot pulse
<3> Mode 2: Frequency generator
<4> Mode 3: Square wave generator
<5> Mode 4: Software Trigger strobe
<6> Mode 5: Hardware trigger strobe
(24) Assuming that the input clock frequency of the 8253 counter is 2MHZ, in order to generate a square wave output signal of 20KHZ, what is the initial counting value that should be loaded into the counter?
Because the incoming initial value is 100
2 MHZ 20 KHZ = 100 \frac{2MHZ}{20KHZ}=10020 KHZ _2 M H Z=100
(25) Set the IO port address of 8253 to 300H~303H, and try to program the three counters of 8253, so that counter 0 works in mode 1, and the initial counting value is 8253H; counter 1 works in mode 2, and the initial counting value is 7788H; Counter 2 works in mode 3, and the counting initial value is 1000.
(1) First of all, we need to know that there are 4 IO ports of 8253, and the default is channel 0, channel 1, channel 2, and control port from small to large.
(2) The control word of 8253 is as follows. In order to prevent some people who don't know much about it, let me explain some of the meanings of these control words.
<1>8253 has 3 counters, which can be selected according to the situation.
<2> The counter has 4 states, if it is latched, it will not count. If it is 01, then only the lower 8 bits are counted. If it is 10, then it is counting with eight digits. If it is 11, then it is 16 bits for counting. (Note: This is a bit like TI's chip. The timer is divided into timer A and timer B. Timer A and timer B respectively represent the high and low 8 bits of a 16-bit timer, but in order to obtain a larger counting range. Generally, timer A and timer B are combined into one, which is equivalent to writing 1 in D5 and D4 here)
<3>8253 has 6 working modes, as in the above question.
<4> What is the difference between the last binary count and the BCD code count? Very simple, if we write 1234 to the register, if D0 is 0, then 1234 is a hexadecimal number, which is 4660 in decimal. If it is BCD code counting, that is, D0 is 1, then 1234 in the register is decimal.
(4) With the pre-foundation, we can start writing programs now.
<1>Because we need to control the counter 0. So D6 and D7 are 0.
<2>Because the 8253H cannot store 8-bit data, D5 and D4 are 1.
<3> Because mode 1 is required, D3-D1 is 001.
<4>8253H is a hexadecimal number, so we write 0 in D0 here.
<5> After writing the control word, it is necessary to transfer the counting initial value 8253H to the counter 0. Note that here you need to write the lower 8 bits first, and then write the upper 8 bits.
MOV DX,303H
MOV AL,00110010B
OUT DX,AL ;设置计数器0工作于方式1，二进制计数
MOV DX,300H ;因为计数器0为最小地址
MOV AX,8253H
OUT DX,AL ;先写入低八位，控制字中规定的
OUT DX,AH
(5) According to the above routine, it is obviously very simple.
<1> Counter 1 works in mode 2, then the control word should be 0111 0100B or 0111 1100B. Because the mode 2 of the control word stipulates that D3 can be any value.
<2> The writing method of initial value 7788H is as above
MOV DX,303H
MOV AL,01110100B
OUT DX,AL ;设置计数器1工作于方式2，二进制计数
MOV DX,301H ;计数器1的地址
MOV AX,8253H
OUT DX,AL ;先写入低八位，控制字中规定的
OUT DX,AH
(6) Still follow the above routine.
<1> Counter 2 works in mode 3, then the control word should be 1011 0111B or 1011 1111B. Because the mode 2 of the control word stipulates that D3 can be any value. It should be noted here that the written data is in decimal, so D0 is 1.
<2> The initial value of 1000 is written as above
MOV DX,303H
MOV AL,10110111B
OUT DX,AL ;设置计数器2工作于方式3，BCD计数
MOV DX,302H ;计数器2的地址
MOV AX,1000
OUT DX,AL ;先写入低八位，控制字中规定的
OUT DX,AH
(26) What are the two types of interrupts of the 8086 CPU? What are hardware interrupts and software interrupts? What is the difference between the two processes in PC?
(1) Hardware interrupt, software interrupt.
(2)
<1>Hardware interrupt is to request the processor to perform interrupt service by inputting electrical signals through the interrupt request line.
<2>Software interrupt is an interrupt process that is recognized and processed inside the processor.
(3)
<1>The hardware interrupt is generally provided by the interrupt controller to provide the interrupt type code, and the processor automatically turns to the interrupt handler
; No external information is required.
(27) What is a non-maskable interrupt? What is a maskable interrupt? What are the conditions for them to get a response from the CPU?
(1) Non-maskable interrupt: The interrupt request introduced by the NMI pin that is not affected by the interrupt enable flag bit IF is a non-maskable interrupt.
(2) Maskable interrupt: The interrupt request introduced by the INTR pin and affected by the interrupt enable flag bit IF is a maskable interrupt.
(3) As long as the effective width of the request pulse on the NMI is greater than two clock cycles, the CPU can latch the request signal. When the CPU samples a transition signal from low to high on the NMI, it will automatically enter the NMI interrupt service routine. For maskable interrupts, the CPU will decide whether to respond according to the status of the interrupt enable flag bit IF. If IF=0, the CPU ignores the interrupt request and continues to execute the next instruction; if IF=1, the CPU will transfer to the interrupt response cycle after executing the current instruction.
(28) What is the interrupt type number? What is an interrupt vector? What is the interrupt vector table? In the microcomputer system based on 8086CPU, what is the relationship between the interrupt type number and the interrupt vector?
(1) Interrupt type number: the code assigned by the system to each interrupt source
(2) Interrupt vector: a default memory area that stores the entry addresses of all types of interrupt handlers.
(3) Interrupt vector table: Store all system interrupts and their corresponding interrupt vectors in one area according to certain rules.
(4) In the 8086CPU, the relationship between the interrupt type number and the interrupt vector: multiply the interrupt type number by 4 to get the entry of the vector table.
(29) What is an interrupt source? What is interrupt priority? What is interrupt nesting?
(1) Interrupt source: The event that caused the interrupt
(2) Interrupt priority: The interrupt is divided into several levels according to the priority called interrupt priority
(3) Interrupt nesting: The interrupt source with high interrupt priority is allowed to interrupt the low priority that is being executed A level interrupt service routine is called interrupt nesting.
(30) How many levels of interrupts does the 8086CPU have in total? What are their interrupt type numbers? Where is the interrupt vector table located in the memory area?
(1) 256-level interrupt
(2) The interrupt type number is 0~255
(3) The interrupt vector table is stored starting at memory 0, and stored in 1024 units from 0000:0000 to 0000:03FF.
What are the 4 working modes of DMA controller 8237A? What are the characteristics and application occasions of various working methods?
<1>Single-byte transmission mode: 8237A releases the system bus after each byte transmission is completed.
<2>Block transfer mode: multiple bytes can be transferred continuously, only when the byte counter is reduced to zero, the bus is released and the transfer ends.
<3> Request transmission mode: only after each byte is transmitted, if it is detected that the DREQ terminal becomes an inactive level, the transmission will stop, and when the DREQ becomes an active level again, the transmission will continue on the original basis.
<4> Cascading transmission mode: Several 8237A can be cascaded to form a master-slave DMA system, and a maximum of 5 8237A can form a secondary DMA system to obtain 16 DMA channels. The mode register is set to the cascade transfer mode, and the slave chip does not need to set the cascade mode.
(31) What kinds of data transmission methods are there in serial communication, and what are their characteristics?
(1) Simplex, half-duplex and full-duplex.
(2) Simplex transmission: There is only one communication transmission line, and data is only allowed to be transmitted in one fixed direction. That is to say, one party can only be the data sender, and the other party can only be the data receiver.
(3) Half-duplex transmission: There is only one communication transmission line, and both parties in the communication have the ability to receive and send data. But this method can only use time-division multiplexing to transmit data, that is to say, data can only be transmitted in one direction at the same time. To realize two-way transmission of data, sending and receiving can only be carried out alternately.
(4) Full-duplex transmission: There are two communication transmission lines, both communication parties can send and receive data at the same time, both communication parties have independent transmitters and receivers, and each has a transmission line to connect them, thus overcoming simplex and half The duplex method brings the disadvantage that both parties cannot send and receive data at the same time.
(32) What is the difference between full-duplex and half-duplex communication? Can full-duplex communication be performed on a two-wire circuit?
(1) Half-duplex data transmission allows data to be transmitted in two directions, but, at a certain moment, only allows data to be transmitted in one direction, it is actually a simplex communication that switches directions. Whereas, full-duplex data communication allows data to be transmitted in both directions simultaneously.
(2) No, full-duplex communication cannot be performed on a two-wire circuit, and only single-ended transmission or reception is possible. Because one signal line and one ground line can only transmit in one direction at the same time.