Structural statement

initial

Execute only once

initial begin
    sys_clk 	<= 1'b0;
    touch_key	<= 1'b0;
    #20		sys_rst_n 	<=  1'b0;
    #110	sys_rst_n 	<=  1'b1;
end

always

Repeat while(1) all the time

always #10 sys_clk <= ~sys_clk  //产生20ns周期时钟信号

always can be edge-triggered or level-triggered

always @ (sensitive list)

The sensitive list is similar to while (judgment statement)

For example:

always @(posedge sys_clk or negedge sys_clk) begin  //边沿触发 描述时序逻辑
    if (!sys_clk)
        count <= 24'd20;
    else if (count <= 24'd20)
        count <= 24'd25;
end

always @(a or b or c or d) begin  //电平触发 描述组合逻辑
    a <= a | b ;
end

always @(*) begin  // 对所有输入变量都是敏感的
    a <= a | b ;
end

assignment statement

blocking assignment

In an always, subsequent statements start after the previous statement ends.

When an assignment is performed, the RHS (the one on the right side of the equal sign) is calculated and the LHS (the one on the left side of the equal sign) is updated.

b = a;

non-blocking assignment

Multiple statements calculate the RHS at the same time, and update the LHS at the same time after the calculation.

Non-blocking assignment intelligence assigns values to register types, REG.

b <= a;

Instructions

Combination logic uses blocking assignment "="

Temporal logic uses non-blocking assignment "<="

In the same always block, do not use blocking and non-blocking at the same time;

It is not allowed to assign a value to the same variable in multiple always blocks;

Conditional statements

IF statement

### IF
if(XXX)
XXX;

### IF-ELSE
if(XXX)
XXX;
else
xxx;

### IF-ELSEIF
IF(XXX)
XXX;
else if (XXX)
XXX;
else if (XXX)
XXX;

Conditional statements must be in initial and always blocks

other

0, X, Z are judged as false; 1 is true

The operation statement after if can be a block statement composed of begin+end, which is equivalent to braces

CASE statement

case (num)
	4'h0	:	seg_led <= 8'b1100_0010;
	4'h1	:	seg_led <= 8'b1100_0011;
	default	:	seg_led <= 8'b1100_0111;
endcase

The values of the branch expressions must be different (4'h0 4'h1 ...)
All expressions must have the same bit width, and the bit width must be specified
casez, regardless of high resistance value Z
casex, regardless of high resistance value Z and indeterminate value X

Verilog learning (2) advanced knowledge points