Eleven, even frequency division--two frequency division | four frequency division | eighth frequency division
All frequency dividers are actually a kind of counter circuit. This article mainly talks about this type of topic.
11.1 Topic description and analysis
Realize two frequency division | four frequency division | eight frequency division circuit, satisfying 50% duty cycle.
1. The register cascading method can realize 2^N even frequency division. Specifically, a circuit with a register structure is used. Whenever the rising edge of the clock arrives, the output result is reversed to achieve even frequency division.
2. The counter method can realize any even frequency division. Taking the eighth frequency division as an example, what the circuit needs to realize is: the counter starts counting from 0 to 3, and when the rising edge of the clock reaches clock=3, the output clock is reversed .
Here we use the register cascading method to achieve. (The output of one flip-flop is used as the clock of the next flip-flop)
11.2 Register realizes 2^N even frequency division
module even_divide(clk,rst_n,clk2,clk4,clk8);
input clk;
input rst_n;
output reg clk2;
output reg clk4;
output reg clk8;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
clk2 <= 1'b0;
else
clk2 <= !clk2;
end
always@(posedge clk2 or negedge rst_n)
begin
if(!rst_n)
clk4 <= 1'b0;
else
clk4 <= !clk4;
end
always@(posedge clk4 or negedge rst_n)
begin
if(!rst_n)
clk8 <= 1'b0;
else
clk8 <= !clk8;
end
endmodule
12. Arbitrary even number frequency division - duty cycle 50%
12.1 Topic description and analysis
Implement a divide-by-6 circuit with a duty cycle of 50%.
It can be seen from the above analysis that the counter method can realize any even frequency division.
Taking the frequency division by six as an example, what the circuit needs to realize is: the counter starts counting from 0 to 3=2, and when the rising edge of the clock reaches clock=2, the output clock is reversed.
12.2 Counter method to achieve six frequency division
module moduleName (
input clk,
input rst_n,
output reg clk_6
);
reg [1:0] cnt6;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt6 <= 2'd0;
else if(cnt6 == 2'd2)
cnt6 <= 2'd0;
else
cnt6 <= cnt6 + 2'd1;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
clk_6 <= 1'b0;
else if(cnt6 == 2'd2)
clk_6 <= ~clk_6;
else
clk_6 <= clk_6;
end
endmodule13. Odd frequency division - no duty cycle required
The duty cycle is not required, which is easier to achieve. For example, to achieve a frequency division by five, you can count 5 clock cycles, such as 1 high and 4 low, 2 high and 3 low, and so on.
Another example. As shown in the figure, it can be found that if Clock is the input clock signal and Clock2 is the output 50% duty cycle three-frequency signal, then for the counter, the operation implemented by Clock2 is: when the sampling edge encounters count=0 every time The time is flipped, and every time 1 is encountered, the flip is completed again. According to this, with the reset signal, we can complete the RTL code.
module moduleName (
input clk,
input rst_n,
output reg clk_5
);
reg [1:0] cnt5;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt5 <= 2'd0;
else if(cnt5 == 2'd4)
cnt5 <= 2'd0;
else
cnt5 <= cnt5 + 2'd1;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
clk_5 <= 1'b0;
else if(cnt5 == 2'd0 || cnt5 == 2'd1) // 这样写是1 - 4 1 - 6 万能写法
clk_5 <= ~clk_5;
else
clk_5 <= clk_5;
end
endmodule14. Odd frequency division - 50% duty cycle
14.1 Topic description and analysis
Realize odd frequency division, 50% duty cycle.
Analysis: If you want to realize a three-frequency clock with a duty cycle of 50%, you can trigger counting by the falling edge of the clock to be divided, and count in the same way as the rising edge for three-frequency division, and then the three-frequency clock generated by the falling edge and Phase-OR operation is performed on the clock generated by the rising edge, and a three-frequency clock with a duty cycle of 50% can be obtained. This method can achieve any odd frequency division.
Classified as a general method : for realizing N times odd frequency division with a duty cycle of 50%, first perform a rising edge trigger for modulo N counting , count to a certain value for output clock inversion, and then pass through (N- 1)/2 is flipped again to get an odd n-frequency clock with a duty cycle other than 50%. (0 is flipped once, (3-1)/2 = 1, flipped once) Furthermore, the modulo N counting triggered by the falling edge is performed at the same time, and the output clock clock is flipped when it reaches the same value as the selected value of the rising edge triggered output clock flip , also after (N-1)/2 , the output clock flips again to generate an odd n-frequency clock with a duty cycle other than 50%. The phase-OR operation of two divided-n clocks with a duty cycle other than 50% results in an odd divided-n clock with a duty cycle of 50%.
It can be understood as generating two n-frequency divisions with a duty cycle other than 50%, and then performing a phase-or operation.
14.2 RTL Implementation of Three-Frequency Division Circuit
module f3(clk, rst_n,clk2);
input clk;
input rst_n;
output clk2;
reg [2:0] negedge_count;
reg [2:0] posedge_count;
reg posedge_clk2;
reg negedge_clk2;
parameter N = 3;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n || posedge_count == N-1)
posedge_count <= 3'd0;
else
posedge_count <= posedge_count +1'd1;
end
always@(negedge clk or negedge rst_n)
begin
if(!rst_n || negedge_count == N-1)
negedge_count <= 3'd0;
else
negedge_count <= negedge_count +1'd1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
posedge_clk2 <= 3'd0;
else if (posedge_count == 3'd1 || posedge_count == 3'd0)
posedge_clk2 <= !posedge_clk2;
else
posedge_clk2 <= posedge_clk2;
end
always@(negedge clk or negedge rst_n)
begin
if(!rst_n)
negedge_clk2 <= 3'd0;
else if (negedge_count == 3'd1 || negedge_count == 3'd0)
negedge_clk2 <= !negedge_clk2;
else
negedge_clk2 <= negedge_clk2;
end
assign clk2 = posedge_clk2 || negedge_clk2;
15. Digital electronic clock
15.1 Topic description and analysis
Essence: It is a counter problem. Recently, Qiuzhao has encountered this written test question several times, but it is actually relatively simple. The key is the writing method of the counter, so I will make a summary. After that, whether it is the autumn recruitment or the written test of the internship interview, try to get this sub-question.
Design a digital clock based on f = 100Hz Clock, implement it with Verilog, and generate hours, minutes, and seconds.
analyze:
The premise is to first multiply the frequency of 100hz to a 1hz clock, so that one beat is 1s.
In fact, it is a carry operation, setting the three carry flags of hour, minute, and second, and clearing the second counter when it is full of 60. When the second counter is full of 60, the minute counter is incremented by 1. When the minute is full of 60 and the second is full of 60, the hour is incremented by 1 and the minute is cleared. When the hour counter is full of 24, and the minute is full of 60, and the second is full of 60, the hour is cleared.
15.2 RTL Implementation
module clock (
input clk,
input rst_n,
output reg[5:0]hour,
output reg[5:0]minute,
output reg[5:0]second
);
// 产生1hz时钟
reg[6:0] clk_cnt;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
clk_cnt <= 0;
else if (clk_cnt == 99)
clk_cnt <= 0;
else
clk_cnt <= clk_cnt + 1;
end
reg clk1;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
clk1 <= 0;
else if(clk_cnt < 50)
clk <= 0;
else
clk <= 1;
end
// 秒模块
always @(posedge clk1 or negedge rst_n) begin
if(!rst_n)
second <= 0;
else if(second == 59)
second <= 0;
else
second <= second + 1;
end
// 分模块
always @(posedge clk1 or negedge rst_n) begin
if(!rst_n)
minute <= 0;
else if((minute == 59)&&(second == 59))
minute <= 0;
else if(second == 59)
minute <= minute + 1;
end
// 时模块
always @(posedge clk1 or negedge rst_n) begin
if(!rst_n)
hour <= 0;
else if((minute == 59)&&(second == 59)&&(hour == 23))
hour <= 0;
else if((minute == 59)&&(second == 59))
hour <= hour + 1;
end
endmodule