Table of contents
How to Constrain Clocks in STA Environment Configuration
1. Specify the clockcreate_clock
● Clock tree: the structure formed by the clock path from the clock source to the CK end of each flip-flop in the sequential circuit.
The main clock for the input and output of the chip port, and the associated clocks such as RXCLK/TXCLK must be create_clockindependently created by the user, and this clock is the starting point of timing analysis.
The configured SDC is as follows
# 名称: SYSCLK
# 周期: 20ns
# 占空比: 20ns内上升沿时刻为0ns，下降沿时刻为5ns
# 端口: SCLK
create_clock -name SYSCLK -period 20 -waveform {
0 5} [get_ports SCLK]
# 名称（默认端口名）: CLKA
# 周期: 20ns
# 占空比（默认-waveform (0,period/2)）: 50%
# 端口: CLKA
create_clock -period 20 [get_ports CLKA]
1.1. Clock Delayset_clock_latency
Divided into network delay and source delay.
● Network latency: It indicates the clock delay from the internal clock definition point of the chip to the CK terminal of the first-stage flip-flop, that is, input2reg.
Source latency (source latency): Indicates the clock delay from the external clock source of the chip (such as crystal oscillator clock, data follow-up clock) to the clock definition point
As shown below.
Theoretically, these clock delays are all 0, and the command can be used in STA set_clock_latency to specify the estimated clock delay values of all endpoints before clock tree synthesis. Once the clock tree is built, this constraint is ignored and actual trace delays are used instead.
Generally, the network delay can be specified, and the SDC is as follows
# 时钟CLK_CONFIG的上升沿和下降沿时钟延迟均为0.8ns
set_clock_latency 0.8 [get_clocks CLK_CONFIG]
# 时钟MAIN_CLK的上升沿时钟延迟为1.8ns
set_clock_latency 1.8 -rise [get_clocks MAIN_CLK]
# 所有时钟定义的下降沿时钟延迟为2.1ns
set_clock_latency 2.1 -fall [all_clocks]
# 时钟SYS_CLK的上升沿和下降沿源时钟延迟均为1.9ns
set_clock_latency 1.9 -source [get_clocks SYS_CLK]
1.2. Clock Uncertainty (Clock Jitter)set_clock_uncertainty
There is a certain degree of jitter in the period of the clock signal coming out of the PLL.
Of course, ideally, the jitter is 0, and a time window can be set by the STA instruction, and a clock edge may be generated at any time within this window, and such a time window can represent the amount of jitter.
As shown below
Clock jitter will increase the requirements for setup time margin and hold time margin, so it is divided into setup uncertainty and hold uncertainty.
As shown in the figure below, effective clock period is the expected clock edge position established according to the clock definition, setup uncertainty is the uncertainty earlier than the scheduled clock edge, and hold uncertainty is the uncertainty later than the scheduled clock edge
The SDC command is as follows
# 时钟CLK_CONFIG的setup uncertainty
set_clock_uncertainty -setup 0.2 [get_clocks CLK_CONFIG]
# 时钟CLK_CONFIG的hold uncertainty
set_clock_uncertainty -hold 0.05 [get_clocks CLK_CONFIG]
# 时钟SYS_CLK到CFG_CLK的跨时钟路径的hold uncertainty 为0.05ns
set_clock_uncertainty -from SYS_CLK -to CFG_CLK -hold 0.05
# 时钟SYS_CLK到CFG_CLK的跨时钟路径的setup uncertainty 为0.1ns
set_clock_uncertainty -from SYS_CLK -to CFG_CLK -setup 0.1
● Clock skew (clock skew): The time difference between the clock signal arriving at different terminals from the clock source PLL. Clock skew is caused by clock delay and clock jitter.
1.3. Clock Transition Timeset_clock_transition
Refers to the time required for the clock to go from the start point to the end point of the threshold voltage. Slew rate (Slew rate) is the reciprocal of transition time.
The command is as follows
# 时钟CLK_CONFIG的上升沿过渡时间为0.1ns
set_clock_transition -rise 0.1 [get_clocks CLK_CONFIG]
# 时钟CLK_CONFIG的下降沿过渡时间为0.12ns
set_clock_transition -fall 0.12 [get_clocks CLK_CONFIG]
Of course, in actual simulation and analysis, the ideal waveform as shown in the figure below is often used directly for timing analysis, and the level conversion time is approximated to zero.
2. Derived clockscreate_generated_clock
Use the clock generated by the specified clock ( create_clockthe clock generated by the instruction) through MMCM/PLL/BUFR, or the clock designed by the user, and the derived clock needs to be constrainedcreate_generated_clock
4.1 Verilog synchronous and asynchronous
in-depth analysis of the difference between Create_clock and Create_generated_clock
The command is as follows
# 名称: CLKP
# 周期: 10ns
# 占空比: 50%
# 端口: UPLL0/CLKOUT
create_clock -name CLKP -period 10 [get_pins UPLL0/CLKOUT]
# 名称: CLKPDIV2
# 源时钟: UPPL0/CLKOUT
# 分频系数: 2
# 端口: UFF0/Q
create_generated_clock -name CLKPDIV2 -source [get_pins UPLL0/CLKOUT] -divide_by 2 [get_pins UFF0/Q]
If the derived clock has multiple sources, you need to specify which is the source clock.
3. Define the clock domainset_clock_groups
Multiple clocks can be grouped into groups, usually asynchronous between clock groups.
# CLKA和CLKB为同步时钟，且与CLKC异步
set_clock_groups -asynchronous -group {
CLKA CLKB} -group {
CLKC}
# CLKA和CLKB为同步时钟，且与CLKC以及CLKC的衍生时钟 异步
set_clock_groups -asynchronous -group {
CLKA CLKB} -group {
[get_clocks -include_generated_clocks CLKC]}
If the two clocks do not need to perform STA, but both clocks come from the same line, logic isolation is required, as shown in the figure below
# C1和C2为来自同一根线，但相互之间不需要STA
set_clock_groups -logically_exclusive -group C1 -group C2
If two clocks need to perform STA, but both clocks come from the same line, logic isolation is required, as shown in the figure below