STA: timing check - input2output type

As one of the four timing paths to be analyzed by STA, it can be regarded as a variant of reg2reg. For details, see STA: Timing Check

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4. input2output

The fourth is that both the launch trigger and the capture trigger are outside the chip.

The path from initiating trigger to capturing trigger is as follows:

Parameter definition:

● $T_{clk2INB}$: The delay of rising edge transfer from clock CLKM to port INB through flip-flop UFF0.

is the input path delay of port INB relative to clock CLKM, that is, $T_{clk2INB}=T_{clk2UFF}+T_{CK2Q}^{UFF}+T_{UFF02I}$, specified by the SDC below

# 最长路径，用于建立时间检查
set_input_delay -clock CLKM -max 1.5 [get_ports INB]

# 最短路径，用于保持时间检查
set_input_delay -clock CLKM -min 1 [get_ports INB]

● $T_{INB2POUT}$: The delay of data from the design port INB, through a series of combinational logic elements, and finally to POUT

Depending on the combinatorial logic between ports INB to POUT after synthesis, the combinatorial logic delay is specified by the SDF of the standard cell library.

● $T_{POUT2UFF1}$: The data is output from the design port POUT, passes through a series of combinational logic elements, and finally reaches the delay of UFF1

● $T_{clk2INC}$: Rising edge delay from clock CLKM input through port INC input to design internal.

Here INC is a fixed point for the clock, so the delay is the source delay, which is specified by the SDC below

set_clock_latency 0.8 -source [get_clocks CLKM]

● $T_{INC2PINC}$: The delay of clock CLKM transmission inside the design.

Design the network delay of the internal clock, specified by the SDC below

set_clock_latency 0.2 [get_clocks CLKM]

● $T_{PINC2UFF1}$: Delay of clock CLKM output to UFF1 through port PINC.

● $T_{clk}$: Clock CLKM period, note that this clock is not designed as an internal clock. The value is specified by the SDC below

create_clock -period 10 -name CLKM [get_ports INC]

● $T_{setup\_uncertain}$: The clock CLKM setup time uncertainty, that is, the expected clock edge is ahead of time by a certain period of time.

The value is specified by the SDC below

set_clock_uncertainty -setup 0.3 [get_clocks CLKM]

● $T_{hold\_uncertain}$: Clock CLKM setup time uncertainty, that is, the expected clock edge is delayed for a period of time.

The value is specified by the SDC below

set_clock_uncertainty -hold 0.4 [get_clocks CLKM]

● $T_{setup}^{UFF1}$: UFF1 build time.

● $T_{output}^{UFF1}$: external timing constraints. The difference between the combinational logic delay from POUT to UFF1/D terminal and the combinational logic delay from PINC to UFF1/CK terminal, plus the setup time of UFF1, that is, T output UFF 1 = TPOUT 2 $T_{output}^{UFF1}=T_{POUT2UFF1}-T_{PINC2UFF1}+T_{setup}^{UFF1}/-T_{hold}^{UFF1}$

Can be specified by the following SDC

# 最长路径，用于建立时间检查
set_output_delay -clock CLKM -max 2 [ get_ports POUT]

# 最短路径，用于保持时间检查
set_output_delay -clock CLKM -min 1.5 [ get_ports POUT]

● $T_{setup\_slack}^{UFF02UFF1}$: Setup time margin for paths UFF0-UFF1. is the amount to be calculated, and greater than zero means that the establishment time is satisfied.

● $T_{hold}^{UFF1}$: hold time of UFF1.

● $T_{hold\_slack}^{UFF02UFF1}$: Hold time margin for paths UFF0-UFF1

4.1. Setup time $T_{setup}$examine

STA on capture trigger UFF1

● The time when the data actually arrives at the UFF1/D terminal (Arrival Time): $T_{clk2INB}+T_{INB2POUT}+T_{POUT2UFF1}$

reg2reg型中的Arrival Time为$T_{clk2UFF}+T_{CK2Q}^{UFF}+T_{UFF02UFF1}$, which is equivalent to Arrival Time in input2reg type

● UFF1/D端新信号需要到达的时间（Required Time）：$T_{clk}-T_{setup\_uncertain}+T_{clk2INC}+T_{INC2PINC}+T_{PINC2UFF1}-T_{setup}^{UFF1}$

reg2reg型中的Required Time为$T_{clk}-T_{setup\_uncertain}+T_{clk2UFF1}-T_{setup}^{UFF1}$, equivalent to Required Time in input2reg type

So the setup time margin of UFF1 in path UFF0-UFF1 is:

$$\begin{gathered} 0<T_{setup\_slack}^{UFF02UFF1}=RequiredTime-ArrivalTime \\ =(T_{clk}-T_{setup\_uncertain}+T_{clk2INC}+T_{INC2PINC}+T_{PINC2UFF1}-T_{setup}^{UFF1})-(T_{clk2INB}+T_{INB2POUT}+T_{POUT2UFF1}) \\ =(T_{clk}-T_{setup\_uncertain}+T_{clk2INC}+T_{INC2PINC})-(T_{clk2INB}+T_{INB2POUT})-T_{output}^{UFF1} \\ \text{\hspace{1em}(4.1)} \end{gathered}$$

其中，$T_{setup\_slack}^{UFF02UFF1}$Positive indicates that the timing check has passed.

4.2. Hold time $T_{hold}$examine

STA on capture trigger UFF1

● UFF1/D end old data is actually updated time (Arrival Time): $T_{clk}+T_{hold\_uncertain}+T_{clk2INB}+T_{INB2POUT}+T_{POUT2UFF1}$

reg2reg型中的Arrival Time为$T_{clk}+T_{hold\_uncertain}+T_{clk2UFF}+T_{CK2Q}^{UFF}+T_{UFF02UFF1}$, which is equivalent to the Arrival Time in the input2reg type.
The time when the old data at the UFF1/D end is actually updated is equivalent to the time when the new data actually arrives at the UFF1/D end.

● UFF1/D端旧数据应该更新的时间（Required Time）：$T_{clk}+T_{hold\_uncertain}+T_{clk2INC}+T_{INC2PINC}+T_{PINC2UFF1}+T_{hold}^{UFF1}$

reg2reg型中的Required Time为$T_{clk}+T_{hold\_uncertain}+T_{clk2UFF1}+T_{hold}^{UFF1}$, equivalent to Required Time in input2reg type

So the hold time margin of UFF1 in path UFF0-UFF1 is:

$$\begin{gathered} 0<T_{hold\_slack}^{UFF02UFF1}=ArrivalTime-RequiredTime \\ =(T_{clk2INB}+T_{INB2POUT}+T_{POUT2UFF1})-(T_{clk2INC}+T_{INC2PINC}+T_{PINC2UFF1}+T_{hold}^{UFF1}) \\ =(T_{clk2INB}+T_{INB2POUT})-(T_{clk2INC}+T_{INC2PINC})+T_{output}^{UFF1} \\ \text{\hspace{1em}(4.2)} \end{gathered}$$

其中，$T_{hold\_slack}^{UFF02UFF1}$Positive indicates that the timing check has passed. It can be seen that the hold time margin is independent of the clock period.