design requirements
A complete set of servo control scheme includes the upper computer, integrated drive and control controller and power board. operator
Send various instructions through the host computer, and then the controller executes the corresponding servo function after parsing the instructions, and then controls
The controller transmits the drive signal to the power board drive motor, and finally the controller collects feedback information for closed-loop control and uploads
transfer data.
Combined with the development status and functional requirements of embedded servo controllers at home and abroad, the servo control system in this paper is formulated.
The main functional requirements are as follows:
(
1
) Develop a drive-control integrated control board.
(2) While developing the servo control system of the rigid-flexible coupling platform, the control of the ordinary rigid platform is also taken into account.
(3) Compatible with various digital encoder feedbacks.
(4) Capable of driving
rotary motors and linear motors with a power of less than
1KW .
(5) It can drive two or more permanent magnet synchronous motors.
(6) It can support multiple control modes, such as single closed-loop servo or multi-closed-loop hybrid servo.
(7) Support developers to develop custom control algorithms.
(8) It can support the online control of the supporting host computer, including the control of motor start and stop, reset and zero function and setting
Target control and other functions. Such as setting the target position, target speed and target current, etc.
(9) Collect feedback information and upload it to the host computer for display, such as position information, speed information and current information.
The quality of the control effect involves many factors, and this article focuses on the basic development of the software and hardware architecture.
The purpose is to develop a fully functional drive-control integrated controller. The basic control algorithm adopts the traditional
PID
algorithm.
This more advanced control algorithm is not the focus of this paper.
3.2
Overview of Embedded Systems
Embedded systems are used in more and more fields in today's society
[41]
, ranging from aerospace to wearable
Devices, embedded products can be seen everywhere. Especially its high flexibility, the designer can adjust the
The system adds or deletes functions, making more and more embedded-based product development.
Since the embedded system does not require strong functions and good versatility like the computer system, the embedded system is mainly
A dedicated computer system that is flexibly organized according to user functional requirements. Real projects are often affected by the environment,
Requirements such as cost, power consumption and volume are limited, so many factors have brought about different designs, so that it is difficult
Make a set of solutions suitable for various applications. Therefore, according to the actual needs of the project, the required software can be flexibly tailored.
Hardware modules to form a system that ultimately meets production requirements.
Embedded systems can be summarized into the following stages of development:
The first stage: Embedded systems in this stage mainly focus on the fields of low price and simple functions. Most applications of this system
In low-end occasions, such as simple monitoring functions, indicating functions and industrial control fields with low precision requirements.
The second stage: marked by high-performance embedded kernel and embedded operating system. Low power high performance at this stage
The kernel is capable of running embedded systems and capable of performing complex multitasking events. And the compatibility and extensibility get
Greatly improved, enabling rapid prototyping, shortening development time and reducing costs.
The third stage: the main features of this stage are important breakthroughs in chip manufacturing technology. More and more functions are integrated in a single
A system-on-a-chip is formed in a chip, and the system-on-a-chip is more and more integrated, and the function is reduced while the volume and power consumption are reduced.
stronger. With the rapid development of the Internet, the era of the Internet of Everything is approaching. Technologies such as industrial control and
The combination of the Internet is getting closer and closer, and embedded technology is ushering in a period of rapid development.
The core of the manufacturing industry lies in industrial control, coupled with the rapid development of the industrial Internet and
the popularization of
5G communication
And, the requirements for the real-time and fast response of the operating system are also higher. Therefore, in order to meet the engineering requirements for real-time
In order to meet the security requirements, a suitable real-time operating system needs to be transplanted, and the security and reliability requirements are also increasing day by day.
The working principle of the real-time operating system is roughly to complete the set function within a certain period of time, so it has a high reliability
reliability and real-time. When there is an external emergency or an internal system interruption event, it can quickly respond and deal with it.
reason. It determines the execution order of multi-tasks through the working mode of the task scheduler, judges the status of various tasks and
It enforces urgency, responding as quickly as possible to an event. At the same time, using a real-time operating system can
To divide the project into several independent subtasks, it is very easy to add new functions without major changes,
Greatly simplifies program design and makes program design and extension easy.
3.3
Overall hardware scheme design
3.3.1
Hardware architecture design
The processing accuracy of the current electronics manufacturing industry is constantly improving, whether it is the complexity of the algorithm or the complexity of the processing,
Both bring great challenges to the calculation and control performance of the main control core. previous single control cores such as
ARM
,
DSP
and
Neither
FPGA can fully meet the work requirements alone.
ARM
's specialty is the transaction management function, with the real-time operating system
The system can perform multi-task real-time processing without affecting each other;
DSP
is good at computing power and can quickly process data
processing, encryption and modulation, etc.; the advantage of
FPGA
lies in its strong flexibility and parallel processing capability, which is very suitable for data processing
High speed, hard real-time requirements and communication interface design and other occasions. In order to meet the development needs of the industrial control industry, today
The main control solutions are usually matched with each other to complement each other. At present, the main control architecture of high-end embedded servo controller is mainly
There are the following types:
ARM+DSP
,
DSP+FPGA
and
ARM+FPGA
.
(
1
)
ARM+DSP
architecture. Combining the transaction management function and data processing function,
the CPU
undertakes the task execution
line pressure while
DSP
shares data calculation tasks, ensuring the real-time performance of the system. But it also brings the ability to expand
Poor features, once the allocation of peripheral resources is completed, it will be very troublesome if you want to add new functions in the future, or even just
It can be replaced with a chip with more resources.
（
2
)
DSP+FPGA
architecture.
DSP
is responsible for the algorithm operation function, while
FPGA
is responsible for data acquisition and communication
The interface function transmits the collected data to
the DSP
for unified calculation, and finally
the DSP
outputs the control signal. but disadvantages
It is poor task management ability, which is obviously lacking for the industrial control industry with more and more functions.
（
3
)
ARM+FPGA
architecture. Taking into account both transaction management functions and digital signal processing functions, not only real-time processing
The ability to manage is strong and the scalability is also improved. Nowadays, there are many high-level auxiliary design tools, through high-level language
Or build a model for
FPGA
development, which can effectively simplify
the FPGA
design process. Therefore, in this scheme
FPGA
can replace the data calculation function of
DSP
. After optimization, the calculation time can be faster and real-time
stronger.
Of course, there are also architectures such as ARM+DSP+FPGA
and
SoC
on the market
. These more advanced solutions have no
The query function is more complete and powerful, but the shortcomings are also very obvious. Although taking into account the task processing capability, data
processing power and interface expansion capabilities, but the complexity of the system has also risen linearly, not only taking into account hardware design, but also
To consider software cooperation. On the other hand, it is not cost-effective to consider labor costs and material costs.
Difficulty and maintenance are relatively poor, so these architectures are not considered in this article.
The purpose of the servo control system designed in this paper is to develop a servo system that can adapt to the characteristics of the rigid-flexible coupling platform.
Serving controllers to meet the required functional design and performance testing. By comparing the advantages and disadvantages of various architectures and combining various
Considering the factors, it was finally decided to choose
the ARM+FPGA
architecture as the development object. The specific reasons are as follows:
(1)
The servo control system developed in this paper needs to meet the multitasking function, so
the ARM
main control core is selected
Heart and coupled with a real-time operating system, to meet the functional requirements of the control system.
(2)
In order to adapt the rigid-flexible coupling platform control algorithm, it is necessary to sample multi-channel sensor data synchronously, which requires practical
The importance of timeliness and parallelism. Due to the special structure of
FPGA
, it determines its real-time performance in many main control cores
It can be the strongest, and has the advantages of parallel processing, which meets the functional requirements and expansion requirements of the system.
(3)
The rapid development of semiconductors makes the performance of
the ARM
core stronger and stronger, and the shipments of microprocessors
It is also increasing year by year, and the variety is rich to choose from. The advanced
ARM
core not only greatly improves the working frequency, but also
It also integrates a hard-core floating-point computing unit, so the advanced
ARM
chip has enough performance to process data, and cooperate with
The powerful parallelism and scalability of FPGA meet the performance requirements of the system.
(4)
The last point is to consider the relationship between performance and cost. Common performance brings high cost, and low cost is also limited
controlled performance. High performance and low cost are like fish and bear's paw, you can't have both, so you need to choose a compromise
in the scheme.
After a certain design process, the
ARM+FPGA solution is comparable in function and performance
Advanced solutions such as ARM+DSP+FPGA
or
SoC
, but the cost is much lower.
To sum up,
the ARM+FPGA
architecture is more in line with the servo control system designed in this paper.
3.3.2
Main control chip selection
The main control core is the brain of the entire system and occupies an important position. A suitable main control core will make subsequent development
The development becomes simple and reliable, so it is very important to choose a suitable main control core. However, due to the emergence of various types of microprocessing
There are thousands of types of chips of different brands and series, which brings great challenges to the selection. So
It can be considered from the principles of versatility, cost performance, sustainability, substitution and procurement convenience. a suitable processor
Not only consider its own performance and resource issues, but also need to consider the complete supporting facilities of the processor. Matching of the processor
Facilities include whether the development tools are complete, whether the learning resources are abundant, and whether there are successful implementation examples.
As shown in the picture
*
It shows the domestic market share of microprocessors of major semiconductor manufacturers.
It can be seen from the figure that the company with the highest market share is
ST
, with a market share as high as
21%
. The company's main product is
STM32
series of microprocessors.
STM32
chips can be divided into different series according to different core architectures
,
among which high-performance
M4
and
M7
The kernel series are highly versatile and can replace each other with only a small change.
Moreover, the development environment of
the STM32
chip is relatively complete and mature, not only has a wealth of official manuals and development routines,
And there are also many embedded systems that have been transplanted. Therefore, after various analysis and summary, using
STM32
microprocessing
The microcontroller is a better solution, which can meet the five principles of selecting a microcontroller.
Considering the design requirements, the final selection model is
STM32H743IIT6
chip as the main control core of
the ARM
side
Heart. The chip is a high-performance series product of
the Cortex-M7
core, with rich hardware peripheral resources, and its
With a high-frequency working clock, it can quickly and effectively execute various instructions.
The selection of FPGA chips
is
relatively simple. The world's two
largest
FPGA
manufacturers
Intel
and
Xilinx
The performance of the production benchmark chips is similar, so the main consideration is whether the logic resources are sufficient and choosing a chip that you are familiar with
chip development.
The FPGA chip model
selected in this paper
is
EP4CE22F17C8
. The chip has rich
On-chip resources, memory resources, and multiple global clock networks and phase-locked loops.
3.3.3
Hardware system architecture design
The hardware system architecture can be divided into
ARM
and
FPGA
parts, as shown in
Figure 3-2
.
The FPGA
mainly integrates
Main controller,
FOC
module and feedback module are three major modules. The main controller is responsible for the control of the entire
FPGA
system, each
The parameter setting, drive control and data exchange of each module are handled by the main controller;
the FOC module is the motor
The core algorithm of the control performs coordinate transformation processing and pulse width modulation processing on the sampled current, and finally outputs
The PWM
wave is output to the intelligent power module to control the motor; the feedback module integrates the required encoder types
There are digital encoders and analog encoders respectively. By setting the encoder type and then filtering, the final
After that, the data is sent back to the main controller for unified processing.
ARM
is mainly composed of application layer, driver layer and system layer. Peripherals are connected to the core through high-speed bus.
Control algorithms, communication functions and task management are dealt with. Communication methods include serial port,
RS485
,
CAN
and Ethernet
Four types, for instruction and data transmission with the host computer;
SPI_FLASH
,
EEPROM
and
SDRAM
are used for system tasks
task management, storage system necessary configuration information and a large amount of computing data cache; finally, all task events are handled by
The FreeRTOS
operating system performs unified scheduling.
ARM
and
FPGA
are interconnected and communicated through a bus called Flexible Memory Controller (referred to as
FMC
). Its specific functional block diagram is shown in Figure
3-3
, which includes the controller of commonly used memory chips. controller
The read and write operations of the chip to the storage unit are realized through
the AXI
bus and the
AHB bus.
FPGA
can be seen as
ARM
An external
SRAM
, so
the FPGA can be read and written in
the SRAM
control mode .
FMC
integrates the characteristics of read and write signals of various memory chips, and according to the performance parameters of different memory chips, set
The main time parameters: address setup time, data setup time and address hold time. Cores are used in practical engineering
Chip performance indicators, calculate the required time, and finally set the corresponding registers. In this paper, mode
A
is selected
Timing model, mode
A
supports independent read and write timing control, and its read and write timing is shown in Figure
3-4
and
3-5
.
The main control core used in combination with the hardware solution in this article is
STM32H743IIT6
, so the final choice is more suitable
FreeRTOS
is used as the operating system of this servo controller.
As the name suggests, FreeRTOS
is a free real-time operating system, which is very friendly for a product
, can effectively reduce the cost.
FreeRTOS
has the advantages of being scalable, compact, and easy to use, and it has a variety of
The task scheduling mode, more importantly, the user can artificially assign priority execution to each task according to the real-time degree of the task
Line level, the system can give priority to execution according to the priority of the task, so it is very suitable for industrial control occasions.
3.4.2
Software system architecture design
Figure
3-7
shows the software architecture of the drive integrated controller designed in this paper. The software system from low to high total
It is divided into four levels, and it is not possible to exaggerate layer calls between layers. Moreover, the coupling between each module is low, and the modules provide
The unified
API
interface is called by the upper layer.
The hardware driver layer is used to drive the hardware resources of the board to ensure its normal operation and provide
the API
to the function
can be called by the module. This layer is mainly composed of the communication part and the transaction management part. The servo controller can
Data interaction with the upper computer by means of communication, and the other part is used for system file management, used to save configuration information data
Intermediate variables generated during data and cache operations.
The function module layer includes the implementation of specific function functions, mainly including communication library modules, algorithm library modules, and motor library modules
and upgrade modules. The communication library is used to analyze the communication data frame between the upper computer and the controller, so as to perform corresponding operations
operation; the upgrade module is used to increase subsequent system functions, through remote upgrade of the firmware of the servo controller; the algorithm library model
The block and motor library module contains some advanced motion control algorithms for controlling servo motors, and subsequent development of new
Control algorithms can be directly added to the corresponding library files without affecting other modules.
The system layer uses
the FreeRTOS
real-time operating system, and the task scheduling mechanism is its core technology. exist
The task state in FreeRTOS is always in one of the four states in the figure below, and the switching relationship is shown in the figure
3-8 shown.
The object of the application layer is the operator, and the operator uses the upper layer software to conduct real-time operating system
Task scheduling, and then call the corresponding
API
function, and finally realize the call and drive of the underlying hardware.
The control flow of the entire software system is shown in Figure
3-9
. Start system power-on for initial configuration,
ARM
read
Get
the configuration information in
EEPROM
and
SPI_FLASH ,
The FPGA
chip can
be configured through
ARM or
Configure through the
EPCS
chip; then connect with the host computer to set some parameters in the host computer
Set and then transmit to
ARM
;
ARM then
transmits the current control command to the register of FPGA
through
FMC bus
in the memory module, and then the host controller configures the received data to
each module in
the FPGA ;
Under the control of the step circuit,
the FPGA reads the encoder position signal and current signal synchronously, and then performs coordinate transformation,
Finally modulate the output
PWM
wave; at the same time,
the FPGA
puts the collected data in the register module, and
the ARM
communicates
Read the data in the module through
the FMC
for advanced motion control algorithm operations and return the data to the host
machine for data analysis.