Sequence detection (FSM state machine)

Sequence generation and detection (FSM state machine)

提示：FSM有限状态机，是FPGA和数字IC相关岗位必须要掌握的知识点，在笔试和面试中都非常常见。

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foreword

Written test questions:
1. Understand the state machine: what is a Moore-type state machine, what is a Milley-type state machine, and what is the difference between the two? What is the difference between one-stage, two-stage, and three-stage state machines?

2. Use the state machine to generate the sequence "1101_0110", and output the sequence in a serial cycle;

3. Use the state machine to detect "1101", the serial input test sequence is "11101101011010", the output signal is a valid signal, when detected, the output is high, otherwise it is low, considering the sequence superposition, such as "1101101", then there is Two "1101", namely:

1 1101 101011010, the sequence is detected at the 5th clock, and the next clock outputs a high level;
1110 1101 011010, the sequence is detected at the 8th clock, and the next clock outputs a high level;
111011010 1101 0, at the 13th The clock detects the sequence, and the next clock outputs a high level;

Provide reports in WORD or PDF version, including but not limited to text descriptions, codes, simulation test diagrams, etc.

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1. Basic concept of state machine

State machine : The state machine is composed of state registers and combinational logic circuits, which can be transferred according to the preset state according to the control signal. It is a control center for coordinating related actions and completing specific operations. The finite state machine is called FSM, which is mainly divided into two categories :

1. Moore state machine: the output is only related to the state, that is, it only depends on the current state, and has nothing to do with the input;
2. Mealy state machine: the output is not only related to the state, that is, not only depends on the current state, but also related to the input;

Key point: When realizing the same function, the Mealy type saves one state than the Moore type, and the Mealy type is one clock cycle ahead of the Moore type.

1. One-segment : an always block, which not only describes the state transition, but also describes the input and output of the state, and the current state is output by registers.
2. Two-stage type : two always blocks, sequential logic and combinational logic are separated, one always block uses synchronous timing to describe state transition; the other uses combinational logic to judge state transition conditions, describes state transition rules and outputs, and uses combinational logic to output the current state. Competitive hazards can occur, glitches are created, and constraints are not conducive.
3. Three-stage type : three always blocks, one always block uses synchronous timing to describe state transition; one uses combinational logic to judge state transition conditions and describes state transition rules; the third uses synchronous timing to describe state output and register output.

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2. Use the state machine to generate the sequence "1101_0110", and output the sequence in a serial loop

1. Introduce basic written test questions

1. To generate sequence signal 1101_0111, at least ______ level trigger is required?

   The state of 8bit can be represented by 2^3=8, and at least 3 levels of flip-flops are required.

2. To generate a sequence signal 1101_0111, if a shift register is used , at least ______ level flip-flops are required?

   Requires a level 5 trigger. 11010111 left shift cycle example:
   Level 4: 1101–1010—0101—1011—0111— 1111—1111—1110—1101 , repeated, not allowed Level 5 : 11010—10101—01011—10111—11111—11110—11101— 11010, no repetition, yes.
   

2. FSM generates sequence signals

The code for generating sequence signal 11010110 by cyclic shift is as follows (example):

module  FSM2
(
   input  wire  sys_clk     ,
   input  wire  sys_rst_n   ,
   output reg   data_1 ,
   output wire   data       
);

reg [7:0] data_reg = 8'b1101_0110 ;

always @ ( posedge sys_clk or negedge sys_rst_n ) 
 if( !sys_rst_n ) 
  data_reg <= 8'b1101_0110;
 else  
  data_reg <= {
    
    data_reg[6:0],data_reg[7]};//位拼接符号实现循环移位 
   
assign  data = data_reg[7];//阻塞赋值（=），右侧有变化就立即变化
//非阻塞赋值（<=），右侧有变化，下一个时钟沿变化
always@(posedge sys_clk or negedge sys_rst_n)
    if(!sys_rst_n)
        data_1 <= 1'b0 ;
    else 
        data_1 <= data_reg[7] ;
endmodule

sim simulation code (example):

`timescale 1ns/1ns
module tb_FSM2();
  reg  sys_clk   ;
  reg  sys_rst_n ;
  wire data_1   ;
  wire data;

initial begin
    sys_clk = 1'b0  ;
    sys_rst_n <= 1'b0;
    #30
    sys_rst_n <= 1'b1;
    #800
    $stop;
    end
    
always#10 sys_clk = ~sys_clk;
  
FSM2 FSM2_inst
(
   .sys_clk   (sys_clk  )  ,
   .sys_rst_n (sys_rst_n)  ,
   .data_1    (data_1   )   ,  
   . data     ( data    )  
);
endmodule

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3. FSM sequence detection sequence "1101"

• IDEL: initial state, if 1 is detected, go to S1(1), otherwise keep IDEL;
• S1 (1): If 1 is detected, go to S2 (11), otherwise return to IDEL;
• S2 (11): If 0 is detected, go to S3 (110), otherwise keep S2;
• S3 (110): If 1 is detected, go to S4 (1101), otherwise return to IDEL;
• S4 (1101): If 1 is detected, go to S2 (11), otherwise go back to IDEL.

使用Moore状态机最终输出和输入无关，只要S4有输入就输出1，故采用Moore型三段式FSM有限状态机。

FSM detection 1101 sequence (example):

module  FSM
(
   input  wire  sys_clk     ,
   input  wire  sys_rst_n   ,
   input  wire  data_in           ,
   output reg   data_valid       
);

parameter   IDEL = 5'b00001 ,
            S1   = 5'b00010 ,
            S2   = 5'b00100 ,
            S3   = 5'b01000 ,
            S4   = 5'b10000 ;

reg[4:0] current_state  ;
reg[4:0] next_state     ;
//第一段同步时序逻辑，描述状态切换
  always@(posedge sys_clk)
      if(!sys_rst_n)
          current_state <= IDEL   ;
      else
          current_state <=  next_state ;
//第二段组合逻辑，判断状态转移条件和规律.这里=和<=没区别
    always@(*)
        if(!sys_rst_n)
            next_state <= IDEL  ;
        else 
            case(current_state)
                IDEL    :if(data_in == 1)   next_state <= S1; else next_state <= IDEL;
                S1      :if(data_in == 1)   next_state <= S2; else next_state <= IDEL;
                S2      :if(data_in == 0)   next_state <= S3; else next_state <= S2  ;
                S3      :if(data_in == 1)   next_state <= S4; else next_state <= IDEL;
                S4      :if(data_in == 1)   next_state <= S2; else next_state <= IDEL;
                default : next_state <= IDEL  ;
            endcase
//第三段同步时序逻辑，描述状态输出，Moore型输出：只要S4有输入就输出1
    always@(posedge sys_clk)
        if(!sys_rst_n)
            data_valid <= 1'b0;
        else 
            case(next_state)
                S4      :data_valid <= 1'b1;
                default :data_valid <= 1'b0;
            endcase
endmodule

Sim simulation code, test sequence "11101101011010" for serial input, state machine detects "1101", (example):

`timescale 1ns/1ns
module tb_FSM();
  reg  sys_clk   ;
  reg  sys_rst_n ;
  reg  data_in   ;
  wire data_valid;

initial begin
    sys_clk = 1'b0  ;
    sys_rst_n <= 1'b0;
    data_in <= 1'b0 ;
    #30
    sys_rst_n <= 1'b1;
    #30
    data_in <= 1'b1 ; #20;//延迟是一个周期
    data_in <= 1'b1 ; #20;
    data_in <= 1'b1 ; #20;
    data_in <= 1'b0 ; #20;
    data_in <= 1'b1 ; #20;
    data_in <= 1'b1 ; #20;
    data_in <= 1'b0 ; #20;
    data_in <= 1'b1 ; #20;
    data_in <= 1'b0 ; #20;
    data_in <= 1'b1 ; #20;
    data_in <= 1'b1 ; #20;
    data_in <= 1'b0 ; #20;
    data_in <= 1'b1 ; #20;
    data_in <= 1'b0 ; #20; 
    #150
    $stop;
    end
    
always#10 sys_clk = ~sys_clk;
  
FSM  FSM_inst
(
   .sys_clk   (sys_clk   ) ,
   .sys_rst_n (sys_rst_n ) ,
   .data_in   (data_in   ) ,
   .data_valid(data_valid) 
);
endmodule

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Summarize

• 在序列产生处：通过位拼接符号实现循环移位
• 在序列产生处：阻塞赋值和非阻塞赋值的区别，两个信号都进行了对比
• 在序列检测处：三段式状态机写代码的特点
• 在序列检测处：第三段时，Moore状态机和Mealy状态机输出的区别

At the beginning, the simulation effect was not correct, and finally found that the delay after the data_in input was not synchronized with the clock cycle, not 20ns.