Overview - What is the finite state machine FSM
Finite state machine -Finite State Machine, abbreviated as FSM, is a mathematical model of the behavior of a finite number of states and transfer and action between these and other states, has been widely used in the computer field. FSM typically contains several elements: triggering state management, status monitoring, state, triggered by the state to trigger actions.
The following is a wiki about the FSM description, link address for the Finite State Machine-WiKi .
A finite-state machine (FSM) or finite-state automaton (plural: automata), or simply a state machine, is a mathematical model of computation used to design both computer programs and sequential logic circuits. It is conceived as an abstract machine that can be in one of a finite number of states. The machine is in only one state at a time; the state it is in at any given time is called the current state. It can change from one state to another when initiated by a triggering event or condition; this is called a transition. A particular FSM is defined by a list of its states, and the triggering condition for each transition.
Two forms of FSM
For FPGA hardware circuit, regardless of what kind of state machine, we assume that F is a function of the current state and input signals. State machine are output, G is a function of the current state and the input signal provided by the output of combinational logic G. Then for the logic of the state machine, it can be expressed as follows:
下一个状态 = F(当前状态，输入信号);
输出信号 = G(当前状态，输入信号);In the state machine, based on the relationship we state machine output and input of the state machine is divided into two models, which are state machines Mealy and Moore state machine. Detailed below these two parts.
Moore state machine
Moore state machine is a sequential logic output depends only on the current state of the state machine type. At this time, the output expression is 输出信号 = G(当前状态，输入信号);this.
Moore state machine clock synchronization structure as shown below, can be seen from FIG logical G whose output is determined only by the current state.
Mealy state machine
Mealy state machine is a sequential logic output depends not only on the state but also on the input a state machine type. At this time, the output of the state machine which expression is 输出信号 = G(当前状态，输入信号);this.
Mealy state machine clock synchronization structure as shown below, can be seen from FIG logical G whose output is determined by the input and with the current state.
Moore vs Mealy state machine
Mealy machine than the Moore machine "in response" fast.
Mealy machine with the output of the current state and input, whereas only the Moore machine outputs related to the current state. Mealy machine immediate response input in the current cycle; Moore machine input influence the next state, the next state by affecting the output. Mealy machine than that end of the output sequence ahead of a Moore machine cycle, i.e., "response speed" fast. Mealy machine output in the current cycle, a longer path (combinatorial logic); Moore machine output having a delay time period, the clock synchronization readily available, Moore machine with good timing.
Less Mealy state machine, Moore machine structure is simple.
Since the output of only the current state of the Moore machine related to an output corresponds to a state, Moore machine has more states. Between Mealy and Moore machine can be transformed into each other, for each Mealy machine, Moore machine has an equivalent, the upper limit of the number of Moore state machine and the output product of the number corresponding to the Mealy state machine.
State machine to trigger a reaction by the number, Mealy state machines with smaller, with less trigger for this purpose.
Moore and Mealy state machines interchange of
For a given sequential logic functions can be implemented with a Mealy machine, Moore machine can be implemented. The characteristics of a Moore machine cycle than the backward output Mealy machine, conversion between the two state machines may be implemented. Converting Moore machine approach is to Mealy machine, the output state of the secondary current corresponding to modify the output state, a state concomitant with an equivalent number of properties. Mealy machine to convert Moore machine approach is to modify the output of the current state of a corresponding output sub-state, while adding some status. As shown below, the Mealy state map is converted to Moore state machine of FIG.
As shown above, the conversion Mealy type machine is the Moore machine type, as long as the current output is changed to the next output timing. For state A, there are four arrow pointing to it, four states can be expressed to the next state in the current state of A; current outputs are simultaneously 0, 0 can move inside status A, shows a state in the Moore machine a 0 is output. Similarly, it can be shifted respectively 0 B / C state. But for state D, there are two arrows pointing and have different output values need to state D decomposed into two states D1 and D2 (each state corresponds to an output when the output of different status indicates need to use different, i.e. it is the reason Moore machine has more states), to get the full Moore machine state model.
Similarly, if the Moore machine of FIG conversion Mealy machine, Moore machine, as long as the output of the next state is changed to the current state of the Mealy machine output, since the D1 / D2 is in a two-state A / C state between the two, equivalent and the equivalent of a node between the a / C node can D1 / D2 merged into a two-state status.
The state machine design principles
Moore machine and the Mealy machine implementation of the circuit are two different forms of synchronous sequential logic circuit, no functional difference between them, and can be converted to each other. Moore type circuit stable output sequence, the output sequence early Moore Mealy type circuit type circuit generating a clock cycle. In the timing design, according to actual needs, the binding characteristics of the two circuits selected.
For sequential circuit common counter by counter state has been fixed, regardless of type Mealy or Moore type circuit, the same complexity.
In the timing selection circuit design type Mealy and Moore type circuit principle is: when the required output and the desired quick response to the input circuit as simple as possible, selection Mealy type circuit. When the output is stable timing requirements, the output sequence can accept one cycle later, and Moore type selection circuit without increasing the complexity of the circuit, appropriately selected Moore type circuit.
Moore state machine
3-stage state machine (recommended)
A - Normal
// 第一个always块，描述当前状态的状态寄存器，non-blocking
always @ (posedge clk or negedge rst_n) begin
if (!rst_n)
curr_state <= idle;
else
curr_state <= next_state;
end
// 第二个always块，描述状态转移，即下一状态的状态寄存器，blocking
always @ (*) begin
next_state = idle; // 初始化
case (curr_state)
idle: begin
if (...)
next_state = sx;
else
next_state = sy;
end
...
default:
next_state = sz;
endcase
end
// 第三个always块，组合逻辑描述输出，blocking
always @ (*) begin
if (!rst_n) begin
o1 = 1'b0;
end
else begin
case (curr_state)
s1: begin
o1 = 1'b1;
end
...
default: begin
o1 = 1'b0;
end
endcase
end
end
B - improved
// 第三个always块，时序逻辑描述输出，non-blocking
// 此时为时序逻辑
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
o1 <= 1'b0;
end
else begin
case (curr_state) // 注意此处为当前状态
s1: begin
o1 <= 1'b1;
end
...
default: begin
o1 <= 1'b0;
end
endcase
end
end
C - improved
// 第三个always块，时序逻辑描述输出，non-blocking
// 此时为时序逻辑
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
o1 <= 1'b0;
end
else begin
case (next_state) // 注意此处为前一状态
s1: begin
o1 <= 1'b1;
end
...
default: begin
o1 <= 1'b0;
end
endcase
end
end
Reference thanks
[1] The two types of state machines