Verilog state machine tips

  "Nothing difficulty is increased by a state machine can not be resolved, if not, then two .."

  When implementing a certain function, if the various functions of sensation is possible to switch between states too around this time, increase the number of state machines can often become clear thinking, will realize the function of the simple.

  The reason for this phenomenon is due originally to be implemented features include a small function of each interrelated functions is of relevance, to implement a state machine code will be written in a very awkward.

  If the individual small independent function independently of each other into a state machine, and to realize the connection between these functions through a small overall state machine, the code becomes simple and clear, mainly to help writers sort out our thinking, without having to do something curved around to ask for it.

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Origin www.cnblogs.com/achangchang/p/11237204.html