Design Process and Tools
Design Flow
The RTL level describes the circuit, logic synthesis, technology mapping, place and route, and generate configuration data.
HDL-based design process
1. The creation of the project
includes source program, setting file, constraint file, etc.
2. The creation of the source file
is to add the circuit description code to the source file
3. The creation of the simulation source file
In addition to the source file, the test file testbench is also added. If IP is used, the behavior model of IP needs to be added.
4. Logic synthesis
Generate a netlist file from the RTL description
5. Technology mapping
Map the netlist file to the actual logic elements of the FPGA (such as a lookup table)
6. Layout and routing
Use on-chip resources to implement the netlist, and it may not be possible to configure the same, so it is necessary to redesign the architecture and algorithm or replace the device.
7. Configure FPGA
to write through JTAG Write
through non-volatile memory Write
through memory card or USB memory
8. Real machine function verification
Select necessary modules to observe the circuit
9. Optimize
operating frequency, circuit scale, power consumption
HLS design
high-level synthesis
1. Behavior synthesis
Generally, variables are mapped to registers, arrays are mapped to memory, functions are mapped to circuit module instances, and flow control such as sequence and branch are mapped to state machines.
Input and output description Bit
width setting
Parallelization description
2. Behavior-level simulation Behavioral
functions can be verified without considering timing, and there may be differences between simulation results and real machines . Determining the running order and running time by two flow graphs is called scheduling, and mapping variables or operations to registers is called binding. Registers and data selectors that implement operations according to a predetermined schedule are called operation paths. Simply put, behavioral synthesis is the mapping of C code into data paths and state machines. 4. Analysis, evaluation and optimization 5. Connection with RTL The modules after behavior synthesis can be connected by instantiation in the upper layer RTL.
Designs Including Processors
FPGA plus processor (combination of hardware and software) can take advantage of hardware and software at the same time. The hard-core processor is the processor implemented on the programmable logic of
the embedded processor soft-core processor FPGA. 1. Build a processor system 2. Develop software for the processor 3. Integration and execution of software and hardware