FPGA (Field Programmable Gate Array), i.e., a field programmable gate array, which is a dedicated circuit (ASIC) in a semi-custom art circuits appear, only solves the problem of custom circuit, and can overcome the existing programming device finite number of gates disadvantages.
FPGA Advantage
(1) run faster
(2) FPGA pin more suitable for large-scale system design
(3) FPGA internal program executed in parallel, high efficiency
(4) FPGA contains a large number of IP cores, facilitate the development of
a flexible (5) FPGA design
FPGA Development Process
(1) Design Specification
(2) Input Design: Schematic design input may be, may be a circuit logic code (Verilog HDL or VHDL) described in
(3) RTL simulation: also known simulation function, primarily used to check the code error codes and the correctness of the behavior
(4) on simulation: converting an input file into a specific gate circuit
(5) place and route
(6), gate-level simulation: the RTL level simulation code is mainly used for error checking and syntax validation logic design is not ideal and the same delay on the delay line between the gate and is not considered; however, gate-level simulation is taken into account, primarily to the actual operation of the digital logic circuit design verification is not meet the design requirements.
(7) Timing Analysis
(8) on the system verifies
FPGA internal structure
（1）
FPGA internal structure comprises six main parts, namely: a programmable IO port input and output, a programmable logic unit, the bottom of the embedded functional unit, the embedded block RAM, and hard core routing resources. The following is the specific introduction.
A programmable input-output ports IO : using software configured without electrical standards and physical properties, such as a pull-down resistor can be adjusted, the matching resistance and other properties, flexible.
Second programmable logic unit : a main programmable logic can be flexibly changed according to the design and configuration of the internal connection to perform different logic functions, FPGA technology is generally based SRAM, a programmable logic unit basically based lookup table LUT (Look-Up-Table) and a number of registers (mainly the D flip-flop) composition.
3 underlayer embedding unit : refers to the FPGA integrated within common high degree of some of the embedded functional blocks, such as phase-locked loop, the DSP and the like.
Routing resources 4 : FPGA internal links all cells, in the actual FPGA placement and routing, quality of layout design features will have a direct impact.
5 Hardcore : This section is relatively small, because the hard core of a single function, not much used in the actual development.
(2)
Supplementary note : the actual development can be appreciated from the four aspects of the internal structure of the FPGA are: configurable logic blocks (the CLB), the input-output block (lOBs), a wiring channel (Routing Channels), programmable switches ( PSW).
In practice, primarily CLB FPGA can be used to measure the number of resources.
CLB mainly comprising a lookup table (LUT) and a D flip-flop, each consisting of a combination of the FPGA logic unit and a timing unit, a digital electronic system designed to make resource preparation.
CLB in the form of a two-dimensional array in the chip, which is called FPGA Field Programmable Gate Array reasons.
CLB generated in the actual digital circuit, using routing resources to connect, when required input or output, can be connected to the CLB input and output modules.
FPGA works
Note: In the following, EDA tools as Quartus II, ISE, Vivado and so on.
The main internal configuration of the FPGA configurable logic block comprising a (the CLB), input and output blocks, and programmable routing resources switch. Wherein the configurable logic block is the main indicator of FPGA resources, in the form of a two-dimensional array chip arrangement.
CLB contains the lookup table and a D flip-lookup table (LUT) logic responsible for providing a composition to the chip, is responsible for providing sequential logic D flip-flops, to provide resources for the design of digital electronic systems.
Lookup table LUT-4, for example, approximately 1 * 16 a RAM, the RAM having a physical structure, but the effect is similar to ROM, various possible operating results of the logic circuit is responsible for storing the generated integrated EDA tools, work FPGA when, according to the data stream input port or a logic flow, the index in RAM the outcome, can be accomplished with a combination of D flip-flops and sequential logic required for digital electronic systems.
When software designers during design time, depending on the design goals, the circuit function described in the form of code out, EDA tools is responsible for the code is compiled and integrated to give the circuit design of a variety of possible outcomes, downloaded to the FPGA, these data CLB are stored in a lookup table. When the system begins to work in the driving data stream or a logic flow, corresponding withdrawn digital logic in the lookup table, and then the D flip-flop with the completion timing of logic design and logic design of digital electronic systems.
So, in some places that based on FPGA LUT technology, in fact, we are the essence of technology-based FPGA SRAM-based FPGA LUT art.
Once the data is loaded into the SRAM cell, he will remain not discharged, but if the entire power supply system off, then, the device configuration data will be lost, which means that such devices need to be reconfigured when the system is powered on. However, this device features can be quickly repeated program, which is then selected SRAM FPGA technology to achieve a lot of reasons.