The basic structure of the FPGA

First, the basic structure of the FPGA
FPGA consists of six parts, namely, a programmable input / output unit, the basic programmable logic unit, the module of an embedded RAM, ample routing, the bottom embedded dedicated hardware functional units and embedded nucleus .
Each unit is described as follows:
1. Programmable input / output unit (I / O units)
Most of the FPGA I / O unit is designed as a programmable mode, i.e., flexible configuration software, can adapt to different standards and electrical I / O physical characteristics; impedance matching characteristics can be adjusted, the pull-down resistor; can adjust the size of the output drive current and the like.
2. Basic programmable logic unit
substantially FPGA programmable logic unit is determined by a lookup table (LUT) and a register (the Register) consisting of the lookup table is completed purely combinational logic function. FPGA internal registers may be configured with a synchronous / asynchronous reset and set, the flip-flop clock energy, may be configured as a latch. FPGA register is completed generally depends synchronous sequential logic design. In general, substantially more classic configuration of the programmable unit is a register plus a lookup table, but the internal configuration registers of different vendors and lookup table there are some differences, and the combination of the mode register and a lookup table are different.
Underlying the importance of a learning unit configured Register and LUT selection device and that the ratio of the size estimate. Since the internal addition to the basic FPGA programmable logic unit, as well as embedded RAM, PLL or the DLL, dedicated Hard IP Core, these modules can be the equivalent of a certain size door system, so a simple scientific method is used number Register or LUT of the device measured.
3. Embedded Block RAM
Most have embedded FPGA block RAM. Embedded block RAM can be configured as a single-port RAM, dual-port RAM, pseudo-dual port RAM, CAM, FIFO storage structure and the like.
CAM, is the content of the address memory. Each CAM data writing and data stored therein may be compared, and returns all data addresses and ports inside the same data. Simply put, a RAM write address and read memory cell data; opposite the CAM and RAM.
In addition to block RAM, Xilinx FPGA and Lattice the LUT can be flexibly configured to RAM, ROM, FIFO storage structure and the like.
4. ample routing
routing resources within the FPGA for all communication units, and the connection process determines the length of the signal transmission speed and the driving capability of the connection. Partitioning routing resources:
1) a global routing resources dedicated: to complete the global clock and the global internal wiring device reset / set; and
2) long-term resource: to complete the number of high-speed signals between the device and some of the second Global Bank wirings (here not know what is the "second global clock signal") clock signal;
3) short-term resource: logic used to complete the interconnection wiring between the basic logical unit;
4) other: internal logic cell also has a variety of and dedicated clock routing resources, reset control signal line.
Because in the design process, automatically tend to select the available routing resources underlying communication unit used by the module layout according to the topology of the logic netlist inputs and constraints, it is often ignored routing resources. In fact, with the use of optimized routing resources and implementation results are directly related.
The underlying embedding unit (cited many examples in the book, but what resources are embedded with the decision on which vendor the stuff of which depends on the specific types of chips)
6. embedded dedicated hard core
and "bottom embedding unit" differentiated, here mainly refers to those hardcore general relatively weak, not all FPGA devices contain a hard core.