Table of contents
1. Part of the code in the design source file
4. Experimental results and analysis
2. Simulation waveform and analysis
(1) Design a sequence detector
(2) Simulation waveform (detection 11010)
3. Download test results and analysis (test 11011)
1. Difficulties encountered in the process of experimental design and solutions
2. The experience of completing the experiment
1. Purpose of the experiment
(1) Master the working principle of sequence generation and detection;
(2) Master the application of state machines in sequential circuits;
(3) Master the design process of implementing complex sequential circuits with Verilog language.
2. Experimental requirements
Design a sequencer and detector:
(1) First realize the design of the serial sequence generator to generate the sequence 0111010011011010; then design the detector, if the serial sequence 11010 is detected, the output is "1", otherwise the output is "0", and it is simulated and hardware Test, select the experimental circuit verification function;
(2) After downloading the program, one LED can be used to serially output the sequence signal, and another five LEDs can be used to observe the sequence to be detected. When all five of 11010 appear on the LED, the identification light M lights up, indicating the detection The signal to "11010" meets the design requirements.
The generated sequence and the detected sequence value ( after the simulation acceptance, the teacher specifies 11011 on site and completes the second acceptance ) .
The generator and the detector are preferably asynchronous to ensure detection, and the clock can be connected to the detector after passing through the NOT gate.
3. Experiment code
1. Part of the code in the design source file
(Note: In order to improve the aesthetics of the experimental report, I have highlighted all the codes if the format meets the requirements)
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`timescale 1ns / 1ps module zhuangtaiji( //模块输入输出 input clk, // 时钟信号 input set, input rst_n, output reg result, output reg seq_out, // 序列输出 output reg led,//一整个序列输出后输出 output reg [7:0]STate ); reg [3:0] state; // 状态寄存器 reg [30:0]fenpin = 0; reg din_vld; // 定义各种状态 parameter S0 = 4'b0000; parameter S1 = 4'b0001; parameter S2 = 4'b0010; parameter S3 = 4'b0011; parameter S4 = 4'b0100; parameter S5 = 4'b0101; parameter S6 = 4'b0110; parameter S7 = 4'b0111; parameter S8 = 4'b1000; parameter S9 = 4'b1001; parameter S10 = 4'b1010; parameter S11 = 4'b1011; parameter S12 = 4'b1100; parameter S13 = 4'b1101; parameter S14 = 4'b1110; parameter S15 = 4'b1111; parameter ST0 = 8'b000_00000; parameter ST1 = 8'b001_00001; parameter ST2 = 8'b010_00011; parameter ST3 = 8'b011_00110; parameter ST4 = 8'b100_01101; parameter ST5 = 8'b101_11011; initial begin state<=S0; STate<=ST0; end // 下面是状态转移逻辑 always @(posedge clk) begin if(~rst_n)//异步清零 begin state<=S0; STate<=ST0; end if(set) begin //if(fenpin==50000000) begin case(state) S0: begin led <=0; state <= S1; seq_out = 1'b1; din_vld = seq_out; end S1: begin state <= S2; seq_out = 1'b1; din_vld = seq_out; end S2: begin state <= S3; seq_out = 1'b0; din_vld = seq_out; end S3: begin state <= S4; seq_out = 1'b1; din_vld = seq_out; end S4: begin state <= S5; seq_out = 1'b1; din_vld = seq_out; end S5: begin state <= S6; seq_out= 1'b0; din_vld = seq_out; end S6: begin state <= S7; seq_out = 1'b1; din_vld = seq_out; end S7: begin state <= S8; seq_out = 1'b1; din_vld = seq_out; end S8: begin state <= S9; seq_out = 1'b0; din_vld = seq_out; end S9: begin state <= S10; seq_out = 1'b1; din_vld = seq_out; end S10: begin state <= S11; seq_out = 1'b1; din_vld = seq_out; end S11: begin state <= S12; seq_out = 1'b0; din_vld = seq_out; end S12: begin state <= S13; seq_out = 1'b1; din_vld = seq_out; end S13: begin state <= S14; seq_out = 1'b1; din_vld = seq_out; end S14: begin state <= S15; seq_out = 1'b0; din_vld = seq_out; end S15: begin state <= S0; seq_out = 1'b1; led <=1; din_vld = seq_out; end endcase endmodule
2. Test file code
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`timescale 1ns / 1ps module testbench()； reg clk; reg rst_n; reg set; wire result; wire led; wire seq_out; wire [7:0]STate; initial begin clk = 1'b0; rst_n = 1'b0; set = 1'b1; #100 rst_n = 1'b1; end always #10 clk = ~clk; //10MHz zhuangtaiji U( .clk(clk), .rst_n(rst_n), .set(set), .result(result), .led(led), .seq_out(seq_out), .STate(STate))； end module
4. Experimental results and analysis
1. Pin lock
set_property PACKAGE_PIN R2 [get_ports set]
set_property IOSTANDARD LVCMOS33 [get_ports set]
set_property PACKAGE_PIN T1 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
set_property PACKAGE_PIN L1 [get_ports seq_out]
set_property IOSTANDARD LVCMOS33 [get_ports seq_out]
set_property PACKAGE_PIN P1 [get_ports led]
set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property PACKAGE_PIN U16 [get_ports result]
set_property IOSTANDARD LVCMOS33 [get_ports result]
2. Simulation waveform and analysis
(1) Design a sequence detector
First of all, it is necessary to clarify the working state and the position of the detector at the next moment when different signals are input, so first draw the sequence detection state transition diagram
(2) Simulation waveform (detection 11010)
As shown in the figure above, after the enable terminal rst_n is enabled, when the sequence "11010" appears, the output bit result shows the detection result, and the sequence "11010" appears three times in the intercepted sequence in the figure, and the result is output. The correctness of the design is verified.
3. Download test results and analysis (test 11011)
Since the sequence detected by the simulation is 11010, and the sequence specified by the teacher is 11011 when the experiment is carried out on the board
First show the simulated waveform
Obviously, after the enable terminal is valid, when the seq_out sequence appears 11011, the output bit result is 1; not only that, due to the particularity of the sequence 11011011011..., in the same sequence, the sequence to be detected will appear two closely spaced apart. Second-rate. Observing the waveform shows that the program has completed the detection and output of the two detection sequences.
Development board experiment results:
The first led light shows the sequence, the light is 1, and the light is 0; the five consecutive leds in the middle indicate the five consecutive numbers of the test sequence, and the last led indicates that if the sequence to be detected is detected, it will be output.
As shown in the figure, the five sequences show the sequence 11011 to be detected, the output bit lights up, and the function design is successful!
5. Experimental experience
1. Difficulties encountered in the process of experimental design and solutions
(1) The sequence detector cannot continuously detect "11011".
Solution: Observing the simulation results, it is found that the detector is directly cleared after each successful detection sequence. Looking back at the program, it is because there is no design for the state transition after the "11011" sequence is detected. Just add this A program, and the state is transferred correctly, the sequence can be continuously detected and successfully output.
(2) The signal of successful detection cannot be output simultaneously with the sequence of 11011.
Solution: Compared with the original sequence, it cannot be output at the same time, so the design sequence s can be converted into a parallel output after a clock signal input sequence is later than the original sequence. Put s and m together in the simulation results, it is easy to observe the results.
2. The experience of completing the experiment
This experiment touched a new content - the design of the state machine. Understanding the transition of the state machine, using the state machine to design a sequence detector, the principle is clear and the design is organized, is a great design method, and the drawing of the state transition diagram is also very interesting. In addition to some code design problems, the difficulties encountered in function implementation are the above two points. Fortunately, they have been resolved in the end, and I understand why this content is designed in this way. Compared with straightforward language descriptions, some skilled programming not only greatly shortens the code length, but also better completes the target function. Every time I see a new programming method, I feel that I still have a long way to go to learn. The completion of each experiment is a new learning journey. Subsequent experiments should become more and more complex, involving more and more content and function realization, but we should still maintain the original enthusiasm, be brave to accept challenges and learn knowledge .
In short , the state machine design experiment is a very important circuit design practice project. In this experiment, I deeply realized the importance of the state machine for hardware circuit design, and also deepened my knowledge of the Verilog HDL programming language. understand.