Table of contents
1. Implementation of state machine
2. The state machine realizes 10010 code detection
1. Implementation of state machine
1.1 Create a project
Create the verilog project file first, and then start the state machine experiment.
1.2 Project Requirements
1. Write a piece of code in verilog according to the following description function, and use the state machine to realize the function.
(1) State machine: implement a test process, which includes 6 states of starting preparation state, starting test, stopping test, querying test results, displaying test results, and returning to initialization at the end of the test; use time to control the process, within 90 seconds Complete the process;
(2) Describe the state jump time;
(3) Coding implementation
2. Draw a state diagram that can detect 10010 strings, and use verilog programming to realize it.
1.3 Code writing
This experiment includes three parts, a counter module, a state machine module, and a top-level module calling the other two parts.
1.3.1 State machine module:
A total of six states
module fsm(
input clk,
input rst_n,
input wire flag
);
reg [2:0] cstate;//当前状态
reg [2:0] nstate;//下一状态
//状态划分
localparam ready = 0;
localparam start = 1;
localparam stop = 2;
localparam query = 3;
localparam display = 4;
localparam initialize = 5;
//初始化
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cstate <= initialize;//复位键被按下，当前状态设置为初始化
else
cstate <= nstate; //下一次状态赋值给当前状态
end
//状态选择
always@(*)begin
if(!rst_n)
begin
nstate = initialize;//初始化
end
else
case(cstate)
initialize: begin
if(flag == 1'b1) //该状态持续时间为1s，1s后，下一次状态更改为led1亮
nstate = ready;
else
nstate = initialize;
end
ready: begin
if(flag == 1'b1)
nstate = start;
else
nstate = ready;
end
start: begin
if(flag == 1'b1)
nstate = stop;
else
nstate = start;
end
stop: begin
if(flag == 1'b1)
nstate = query;
else
nstate = stop;
end
query: begin
if(flag == 1'b1)
nstate = display;
else
nstate = query;
end
display: begin
if(flag == 1'b1)
nstate = initialize;
else
nstate = display;
end
default: ;
endcase
end
endmodule
1.3.2 Counter module
A total of 6 states, switching every 15s
module time_cnt(
input wire clk,
input wire rst_n,
output wire flag
);
parameter MAX_NUM = 30'd749_999_999;//记最大数15s,750_000_000次
reg [29:0] cnt;//计数寄存器
reg flag_r;
//0.5s计时器
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt <= 29'd0;
end
else if(cnt == MAX_NUM)begin
cnt <= 29'd0;
end
else begin
cnt <= cnt + 1'd1;
end
end
//0.5s脉冲信号
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
flag_r <= 1'b0;
end
else if(cnt == MAX_NUM)begin
flag_r <= 1'b1;
end
else begin
flag_r <= 1'b0;
end
end
assign flag = flag_r;
endmodule
1.3.3 Top-level modules
module fsm_top(
input wire clk,
input wire rst_n
);
wire flag;
//例化计时器模块
time_cnt inst_time_cnt(
.clk (clk ),
.rst_n (rst_n ),
.flag (flag)
);
//例化状态机模块
fsm inst_fsm(
.clk (clk ),
.rst_n (rst_n ),
.flag (flag)
);
endmodule
1.4 compile
2. The state machine realizes 10010 code detection
2.1 Create a project
ditto
2.2 Code part
Key debounce
module key_debounce(
input wire clk,
input wire rst_n,
input wire key,
output reg flag, //判断抖动是否消除的标志信号，0为抖动，1为抖动结束
output reg key_value //消抖后稳定的按键值给到蜂鸣器模块和LED模块
);
//定义20ms延迟计数器,0.2s,1_000_000次
reg [19:0] delay_cnt;
//寄存依次key的值用来判断按键是否消抖成功
reg key_reg;
//按下按键20ms延时计数器
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
begin
key_reg <= 1'b1; //复位信号，设置按键无效
delay_cnt <= 1'b0; //计数器设置为0
end
else
begin
key_reg <= key;
if(key_reg ^ key) //当这一次key值和上一次key值不一样，证明正在抖动
delay_cnt <= 20'd1_000_000; //延迟时间20ms
else if(delay_cnt > 0)
delay_cnt <= delay_cnt - 1; //没有抖动，开始20ms倒计时
else
delay_cnt <= 1'b0;
end
end
//根据延时计数器获取按键状态以及按键值
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
begin
flag <= 1'b0; //复位信号，设置信号标志为抖动
key_value <= 1'b1; //设置抽样值为1
end
else
begin
if(delay_cnt == 20'd1) //倒计时1_000_000到1
begin
flag <= 1'b1;
key_value <= key; //稳定20ms后将key值给到key_value
end
else
begin
flag <= 1'b0;
key_value <= key_value; //20ms内先不取样
end
end
end
endmodule
state machine
module fsm_10010(
input clk,
input rst_n,
input [1:0] key,
);
parameter MAX_NUM = 24'd9_999_999;
parameter T = 4'd10;
reg [2:0] cstate; //现态
//状态划分
localparam state_0 = 0;
localparam state_1 = 1;
localparam state_2 = 2;
localparam state_3 = 3;
localparam state_4 = 4;
localparam state_5 = 5;
reg [3:0] cnt = 0;//计时器赋初值为0
reg [23:0] cnt_02 = 0;
reg time_flag;//计时标志，1：开始计时，0：结束计时
//0.2计数器模块
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt_02 <= 1'b0; //按下复位键，清零
else if(cnt_02 == MAX_NUM)
cnt_02 <= 1'b0;
else
cnt_02 <= cnt_02 + 1'b1;
end
//2s计数器模块
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt <= 1'b0;//按下复位键，清零
else if(time_flag == 1'b1)begin//开始计时
if(cnt_02 == MAX_NUM)begin
if(cnt < T)begin
cnt <= cnt + 1'b1;
end
else begin
cnt <= 1'b0;//cnt计数达到最大就清空
end
end
else begin
cnt <= cnt;//其余时间保持
end
end
else begin
cnt <= 1'b0;//不计时，cnt清空
end
end
//状态切换模块
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
begin
cstate <= state_0;
end
else
case(cstate)
state_0: begin
if(key[1] == 1'b1) //该状态持续时间为1s，1s后，下一次状态更改为led1亮
cstate <= state_1;
else if(key[0] == 1'b1)
cstate <= state_0;
else
cstate <= state_0;
end
state_1: begin
if(key[0] == 1'b1)
cstate <= state_2;
else if(key[1] == 1'b1)
cstate <= state_0;
else
cstate <= state_1;
end
state_2: begin
if(key[0] == 1'b1)
cstate <= state_3;
else if(key[1] == 1'b1)
cstate <= state_0;
else
cstate <= state_2;
end
state_3: begin
if(key[1] == 1'b1)
cstate <= state_4;
else if(key[0] == 1'b1)
cstate <= state_0;
else
cstate <= state_3;
end
state_4: begin
if(key[0] == 1'b1)begin
cstate <= state_5;
time_flag <= 1'b1;//开始计时
end
else if(key[1] == 1'b1)
cstate <= state_0;
else
cstate <= state_4;
end
state_5: begin
if(cnt == T)begin
cstate <= state_0;
time_flag <= 1'b0;//结束计时
end
else
cstate <= state_5;
end
default: ;
endcase
end
endmodule
top level module
module fsm10010_top(
input wire clk,
input wire rst_n,
input wire [1:0] key
);
wire [1:0] flag;
wire [1:0] key_value;
//例化按键KEY1
key_debounce inst_key_debounce(
.clk (clk),
.rst_n (rst_n),
.key (key[0]),
.flag (flag[0]),
.key_value(key_value[0])
);
//例化按键KEY2
key_debounce inst_key_debounce1(
.clk (clk),
.rst_n (rst_n ),
.key (key[1]),
.flag (flag[1]),
.key_value(key_value[1])
);
//例化状态机
fsm10010 inst_fsm(
.clk (clk),
.rst_n(rst_n),
.key ({~key_value[1]&&flag[1],~key_value[0]&&flag[0]})
);
endmodule
3. compile
RTL gate circuit
Three summary
Through this fpga experiment, I understand a lot, as well as the future direction, learn slowly and make progress slowly.