The following diagram is an interrupt vector table 2440
We can see that the interrupt vector table is a 4-byte alignment
Which represents the supervisor mode management Mode This mode is equivalent to the administrator mode can access the hardware, if you need to restart crash
undefined mode when the command or address is not defined in the 2440 command interrupt is triggered
FIQ Fast interrupt mode
Normal interrupt mode IRQ
Where you can see an undefined instruction exception is this place 04
1. First, look at the manual
This is after the abort register, wherein the added gray triangles represent only this register is not shared with other registers, but when entering this mode is only used its registers. Such registers are undefined mode own which R13 and R14 are R13 are each stored address the need to deposit the stack in the stack mode. R14 is the address stored exception occurred after that command is used to return to the original R15 is a PC program pointer.
When an exception occurs in the CPU will do the following things (in ARM mode):
1. ARM will automatically put this very next statement to save R14
2. The state of the CPSR to the SPSR before copy
The different abnormal CPSR will change (see below)
4. PC will point to fragment interrupted. .
Program to do is:
1. We need to save the R1-R12 and R14 of the general data and the return data comprises the address of the main program which is stored in the stack
2. In the interrupt processing information (note that R0 and R1 may be stored in the function memory variable inlet C language)
3. All of the data registers pop the stack, the return address R14 to PC
ldr sp, = 0x34000000 // stack to establish
stmdb sp !, {r0, r12, lr} // stack for storing data in
msr r0, cpsr / * reads the value of the CPSR * r0 of /
LDR R1, = und_string
BL print_und
/ ** recovery site ** /
LDMIA SP, {R1, R12, PC} ^ // recovery site