table of Contents
1. External interrupt of STM32F4
1. Number of external interrupts of STM32F4
- Each IO of STM32F4 can be used as an external interrupt input
- But not all IO interrupts can be opened at the same time. STM32F4's interrupt controller can only support **23 (0 ~ 22)** external interrupt/event requests at the same time:
① EXTI line 0 ~ 15: Corresponding to external IO input interrupt (also our commonly used external interrupt interface)
② EXTI line 16: connected to PVD output.
③ EXTI line 17: connected to RTC alarm event
④ EXTI line 18: connected to USB OTG FS wake-up event
⑤ EXTI line 19: connected to Ethernet wake-up event
⑥ EXTI line 20: connected to USB OTG HS (configured in FS) wake up Event
⑦ EXTI line 21: connected to RTC intrusion and timestamp event
⑧ EXTI line 22: connected to RTC wake-up event
For the above 23 external interrupts, each external interrupt corresponds to an external interrupt line, and each external interrupt line can be independently configured with trigger mode (rising edge, falling edge or edge trigger), trigger/mask, and dedicated Status bit .
2. External interrupt for IO port in STM32F4
It can be seen from the above list that the external interrupt lines available for the IO port of STM32F4 are only EXTI lines 0-15 , a total of 16 lines . But STM32F4 has hundreds of IO ports ( (ABCDEFG) 7 x 16 (0~15) ). How to match 16 interrupt lines with hundreds of IO ports ?
The answer is that not all IO ports can trigger interrupts in the program!
Only 16 IO ports that have been configured in advance can cause interrupts in the program. Moreover, it is not an optional 16 IO ports, but 16 IO ports whose IO number (0 ~ 15) must be different, that is, a total of 16 IO ports covering Px 0 ~ 15, where x can be the same , But 0 ~ 15 must be different! Such as PA0, PA1, PA2, PB3, PB4, PC5, PC6, PC7, PC8, PD9, PD10, PD11, PD12, PD13, PD14, PE15.
So, how to realize the configuration of EXTI line 0 ~ 15 and corresponding IO port ?
The answer is through the SYSCFG_EXTICR register. As shown below:
In the figure above, there are 16 external IO interrupt lines EXTI0, EXTI1,..., EXTI15 . Each interrupt line corresponds to a different and fixed 9 IO ports, and one interrupt line can only be connected to each other at a time. One IO port is connected . Take line 0 as an example: it corresponds to GPIOA.0, GPIOB.0, GPIOC.0, GPIOD.0, GPIOE.0, GPIOF.0, GPIOG.0, GPIOH.0, GPIOI.0. The interrupt line can only be connected to one IO port at a time (such as GPIOC.0). This operation needs to be implemented in the software configuration.
3. STM32F4 interrupt service function
As mentioned in the figure above, there are 16 external IO interrupt lines in STM32 , so is there also 16 interrupt service functions?
The answer is no. STM32 has 16 external IO interrupt lines, but only 7 interrupt service functions (or 7 interrupt vectors). As shown below:
That is: EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, the first 5 external IO interrupt lines each have their own independent interrupt function; but EXTI5 ~ EXTI9 share an interrupt function; EXTI10 ~ EXTI15 share an interrupt function.
Second, the writing of STM32F4 external interrupt program
1. Commonly used library functions for external interrupts
In the external interrupt program, the commonly used library functions are as follows: The
basic configuration steps are as follows:
①Enable external interrupt clock:
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
②Initialize the IO port as input:
GPIO_Init();
③ provided interrupt lines IO port mapping relationship, i.e., we are talking about the mapping relationship configured in a **, ** goes FIG 2:
SYSCFG+EXTILineConfig();
④Initialize the online interrupt, set trigger conditions, etc.:
EXTI_Init();
⑤Configure the interrupt group (NVIC) and enable the interrupt: (for the knowledge of interrupt group, please refer to this blog )
NVIC_PriorityGroupConfig //配置中断分组
NVIC_Init(); //使能中断
⑥Write interrupt service function:
EXTIx_IRQHandler();
⑦Clear the interrupt flag bit: ( Note: The interrupt flag bit in the register will not be automatically cleared, and the following function must be used to manually clear it at the end of each interrupt service function execution .)
EXTI_ClearITPendingBit();
2. Press the key to interrupt the programming
3. Complement: the difference between interrupt and event
According to the difference between CSDN blogger [gtkknd] blog post interruption and event :
The simple point is that interrupts must have interrupt service functions, but events do not have corresponding functions.
However, events can trigger other related operations, such as triggering DMA, triggering ADC sampling, etc.
These operations can be performed without CPU intervention.
Interruption requires CPU intervention.
According to the blog post of CSDN blogger [flydream0] STM32 interrupts and events-the difference between interrupts and events :
This picture is a schematic diagram of an external interrupt line or external event line. In the figure, there is a diagonal line on the signal line, and a note with the word 19 is marked next to it, indicating that there are 19 sets of such lines. The blue dashed arrow in the picture, The transmission path of the external interrupt signal is marked. First, the external signal enters from the chip pin No. 1, passes through the edge detection circuit No. 2, enters the interrupt pending request register through the OR gate No. 3, and finally passes the AND gate No. 4 Output to the NVIC interrupt detection circuit. This edge detection circuit is controlled by the rising or falling edge selection register. The user can use these two registers to control which edge is required to generate an interrupt, because the selection of rising or falling edges is subject to two parallel Register control, so the user can select the rising edge or the falling edge at the same time, and if there is only one register control, then only one edge can be selected.
Pressed down is the OR gate numbered 3. The other input of this OR gate is the software interrupt/event register. It can be seen from this that the software can request an interrupt or event prior to the external signal, that is, when the software interrupt/event register corresponds When the bit is "1", no matter what the external signal is, the OR gate of number 3 will output a valid signal.
After an interrupt or event request signal passes through the OR gate numbered 3, it enters the suspend request register. Until then, the signal transmission paths of the interrupt and event are the same, that is, the external signal is recorded in the suspend request register. Level changes.
The external request signal finally passes through the AND gate number 4, and sends an interrupt request to the NVIC interrupt controller. If the corresponding bit of the interrupt mask register is "0", the request signal cannot be transmitted to the other end of the AND gate, which realizes the interruption. shield.
Understand the request mechanism of the external interrupt, it is easy to understand the request mechanism of the event. The red dotted arrow in the figure indicates the transmission path of the external event signal. After the external request signal passes through the OR gate number 3, it enters the AND number 5 Gate, the function of this AND gate is similar to that of the number 4 AND gate, which is used to introduce the control of the event mask register; finally, a jump signal of the pulse generator is transformed into a single pulse, which is output to other functional modules in the chip. From this picture, we can also know that from the perspective of external stimulus signals, the generation sources of interrupts and events can be the same. The reason is divided into two parts, because interrupts require CPU participation, and software interrupt service functions are required. The result generated after the interrupt is completed; but the event is to rely on the pulse generator to generate a pulse, and then the hardware automatically completes the result of the event. Of course, the corresponding linkage components need to be set up first, such as causing DMA operation, AD conversion, etc.;
A simple example: external I/O triggers AD conversion to measure the weight of external objects; if you use traditional interrupt channels, you need I/O triggers to generate external interrupts, the external interrupt service program starts AD conversion, and the AD conversion completes the interrupt service program and submits the final Result: If the event channel is used, the I/O trigger generates an event, and then the AD conversion is triggered by linkage, and the AD conversion completes the interrupt service program to submit the final result; in contrast, the latter does not require software to participate in the AD trigger, and the response speed is also faster; If events are used to trigger DMA operations, some linkage tasks can be completed without software involvement at all.
to sum up:
It can be simply considered that the event mechanism provides a completely automatic hardware trigger to produce a channel, without software participation, reduces the load of the CPU, saves interrupt resources, and improves the response speed (hardware is always faster than software ), is an effective way to use hardware to improve the ability of the CPU chip to process events;
