RISCV Reader
The Birth of RISCV
Distinguished
The purpose of the RISCV architecture is to become a general-purpose instruction set architecture ISA. It not only supports various processors from microcontrollers to high-performance computers, is compatible with various programming languages, but also adapts to all implementation technologies such as FPGA ASIC, stable...
In order to maintain the backward compatibility of the computer architecture when the instruction set is updated, the traditional method is to increase the ISA, and the new processor must implement the new ISA extension and all the old extensions. This is the case with x86, but its disadvantage is that even if the past implementation is wrong, it must be implemented every time for compatibility.
RISCV is modular, the core is RV32I basic ISA, running a complete software stack; other expansion module hardware can be included or not included according to your needs. This makes RISCV lightweight and low energy consumption. For example, to include the three extensions of multiplication RV32M, single-precision floating-point RV32F, and double-precision floating-point RV32D, the name of the instruction set after adding the basic ISA is: RV32IMFD.
7 Metrics in ISA Design
cost
Chips/die are diced from the wafer.
There may be blemishes on the wafer, so the diced die will not be used if it contains blemishes. Therefore, the smaller the grain size, the less the proportion of defects, and the higher the utilization rate. The simpler the ISA, the smaller the die, and therefore the cost.
simplicity
It can be realized by adjusting the instruction. A combination of simple instructions will perform better than complex instructions.
performance
The number of instructions included in the program * the average number of cycles required by the instruction * the time spent per clock cycle = program time.
RISCV has certain advantages in these three aspects.
Separation of Architecture and Concrete Implementation
The specific manifestation is that the architect may include certain instructions in the ISA in order to optimize the performance and cost of a certain part, but this practice may cause a burden to the future implementation; Performance is not necessarily guaranteed. For example, increasing the instruction of the single-issue pipeline may reduce the load of the multi-instruction parallel pipeline and reduce the overall throughput.
Room for improvement
Moore's Law is almost over, and we can no longer expect transistors to double, and there will be more address storage instructions. It should focus on specific areas for improvement, such as machine learning, graphics, AR and other special instructions. Therefore, whether the ISA reserves the opcode space for future improvement is also an important factor to measure.
For example, Thumb2 introduces 16-bit Thumb instructions and Thumb2 with 16+32-bit instructions, and uses a bit mode bit to switch.
program size
Smaller programs require less storage space, and the chip area can also be reduced; and the problem of instruction cache misses will also be reduced (because a total of few instructions are not used), and power consumption will also be reduced. This is not to say that if the instruction is short, the program will be small. On the contrary, the variable-length instruction code of x86 is larger than that of RV32C and Thumb2.
Easy to program/compile/link
On the one hand, we know that the registers in the storage pyramid model are the fastest at the top, so registers should be allocated reasonably. RISCV has 32 of them.
On the other hand, the execution speed of each instruction should remain constant. Under the premise of a cache hit, the RISCV instruction is basically stable and executed in one clock cycle, but for example, the arithmetic operand of x86 may be in the register or in the memory... This kind of operand with an uncertain position, complex instructions make The running speed is not necessarily stable, and performance testing is difficult to guarantee.
book introduction
In the following chapters, RV32I will be introduced first, various RV32G (General) including RV32M, RV32F and RV32D, RV32A atomic operations, 16-bit compression extension RV32C, vector extension RV32V, RV64G, and new extensions under consideration by the RISCV Foundation.