RISCV 6 RISC-V load and store instructions

RISCV - 1 RV32/64G instruction set list
RISCV - 2 "Zicsr", CSR Instructions
RISCV -3 RV32I/RV64I basic integer instruction set
RISCV - 4 ISA extension naming convention
RISCV 5 RISC-V calling rules

1 RV32I Load and Store Instructions

RV32I is a load-store architecture, where only load and store instructions access memory and arithmetic instructions only operate on CPU registers. RV32I provides a 32-bit address space that is byte-addressed. The EEI will define what portions of the address space are legal to access with which instructions (eg, some addresses might be read only, or support word access only). Loads with a destination of x0 must still raise any exceptions and cause any other side effects even though the load value is discarded. RV32I
Yes A load-store architecture in which only load and store instructions can access memory , and arithmetic instructions can only operate on CPU registers. RV32I provides a byte-addressable 32-bit address space. The EEI will define which parts of the address space can be legally accessed with which instructions (for example, some addresses may only allow reading, or only support word access). Loads targeting x0 must still throw any exceptions and cause any other side effects, even if the load value is discarded.
The EEI will define whether the memory system is little-endian or big-endian. In RISC-V, endianness is byte-address invariant
. endian). In RISC-V, byte addresses do not change.
In a system for which endianness is byte-address invariant, the following property holds: if a byte is stored to memory at some address in some endianness, then a byte-sized load from that address in any endianness returns the stored value
. In systems where byte addresses do not change, the following property exists: if a byte is stored at a certain byte address in memory, then a byte-sized load from that address at any byte address will return the stored value .
In a little-endian configuration, multibyte stores write the least-significant register byte at the lowest memory byte address, followed by the other register bytes in ascending order of their significance. Loads similarly transfer the contents of the lesser memory byte addresses to the less -significant register bytes.
In little-endian configuration, multibyte storage writes the least significant register byte to the lowest memory byte address, and then writes the other register bytes in order of increasing most significant bit. When loading, the contents of the smaller memory byte address are also transferred to the least significant register byte.
In a big-endian configuration, multibyte stores write the most-significant register byte at the lowest memory byte address, followed by the other register bytes in descending order of their significance. Loads similarly transfer the contents of the greater memory byte addresses to the less -significant register bytes.
In a big-endian configuration, multibyte storage writes the most significant register byte to the lowest memory byte address, and then writes the other register bytes in descending order of significance. When loading, the contents of the larger memory byte address are also transferred to the smaller register byte.

The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values. The
LW instruction loads 32-bit values ​​in memory into rd. LH loads the 16-bit value from memory, then sign-extends it to 32 bits, and then stores it into rd. LHU loads a 16-bit value from memory but zero-extends it to 32 bits before storing in rd. LB and LBU are defined similarly to 8-bit values. The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-
bit values ​​from the low bits of register rs2 to memory.
The bit value is stored into memory.

1.1 LOAD instructions

Loads are encoded in the I-type format
Load instructions are encoded in the I-type format
I-type instruction encoding format:

1.1.1 Command format of load command

Encoding format of load instructions

The encoding format of the corresponding immediate value is as follows:

• Bit0 of the immediate data is obtained from bit[20] of the load instruction, bits1-4 are obtained from bits[24:21] of the load instruction, and bits 5~10 are obtained from bits[30:25] of the load instruction. Get, the sign bit is the bit[31] of the load instruction, and bit11 ~31 of the immediate value are all sign-extended according to the bit[31] of the load instruction.

1.1.2 Points to note when using the load command

When loading instructions, I type instruction encoding, the immediate value is a signed immediate value, and its sign bit needs to be considered when processing. The range of the immediate value is [-2048 ~ 2047], so when using the load instruction to process offset less than

-2048 And when it is greater than 2047, an abnormal error of offset will be reported. is a
lb t1, (-2048 ~ 2047)(t0)legal load instruction
or an illegal load operation.lb t1, -2049(t0)lb t1, 2048(t0)

1.2 STORE instructions

Stores are encoded in the S-type.
Store instructions are encoded in the S-type.

1.2.1 Instruction format of storage instruction

The instruction format of the storage instruction

The encoding format of the corresponding immediate value is as follows:

• Bit0 of the immediate data is obtained from bit[7] of the load instruction, bits1-4 are obtained from bits[11:8] of the load instruction, and bits 5~10 are obtained from bits[30:25] of the load instruction. Get, the sign bit is the bit[31] of the load instruction, and bit11 ~31 of the immediate value are all sign-extended according to the bit[31] of the load instruction.
  

1.2.2 Points to note when using storage instructions

When storing instructions, the instruction code of type S is used. The immediate value is a signed immediate value. The sign bit needs to be considered when processing. The range of the immediate value is [-2048 ~ 2047].

Therefore, when using the load instruction to process offsets less than -2048 and greater than 2047, an offset exception error will be reported.
sw t1, (-2048 ~ 2047)(t0)is a legal load instruction
, sw t1, -2049(t0)or lb t1, 2048(t0)is an illegal load operation.

2 RV64 Load and Store Instructions

The load and store instructions of RV64 are similar to the load and store instructions of RV32.
RV64I extends the address space to 64 bits. The execution environment will define what portions of the address space are legal to access.
RV64I extends the address space to 64 bits. The execution environment will determine which parts of the address space can be legally accessed.

Load byte (lb): Loads a byte from memory and extends it to 32 bits. For example, lb x1, 0(x2) means loading a byte from the memory location at offset 0 pointed to by register x2, extending it to 64 bits and storing it in register x1.

Load half-word (lh): Loads a half-word (16 bits) from memory and extends it to 32 bits. For example, lh x1, 0(x2) means loading a half word from the memory location pointed to by register x2 at offset 0, extending it to 64 bits and storing it in register x1.

Load word (lw): Load a word (32 bits) from memory. For example, lw x1, 0(x2) means to load a word from the memory location at address offset 0 pointed to by register x2, extend it to 64 bits and store it in register x1.

Load double-word (ld): Loads two words (64 bits) from memory. For example, ld x1, 0(x2) means to load a doubleword from the memory location at address offset 0 pointed to by register x2 and store it in register x1.

Store byte (sb): Store a byte into memory. For example, sb x1, 0(x2) means to store the lower 8 bits in register x1 to a memory location offset 0 from the address pointed to by register x2.

Store half-word (sh): Store half-word in memory. For example, sh x1, 0(x2) means to store the lower 16 bits in register x1 to a memory location offset 0 from the address pointed to by register x2.

Store word (sw): Store a word into memory. For example, sw x1, 0(x2) means to store the value in register x1 to a memory location offset 0 from the address pointed to by register x2.

Store double-word (sd): Store two words into memory. For example, sd x1, 0(x2) means to store the value in register x1 to a memory location offset 0 from the address pointed to by register x2

2.1 Load Instructions

The LD instruction loads a 64-bit value from memory into register rd for RV64I
.

2.2 Store Instructions

The SD, SW, SH , and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values ​​from the low bits of register rs2 to memory respectively. The low-order 64-bit, 32-bit, 16-bit and 8-bit values ​​of rs2 are stored in memory.