Summary of RISC-V architecture and open source processor-based SoC Research

Open source CPU- RISC-V architecture

Scalar processor --Rocket

Rocket is the use of Chisel (Constructing Hardware in an Scala Embedded Language) written

UCB design of a 64-bit, 5-stage pipeline, a single firing sequence executed by a processor, main features are:

Support MMU, paged virtual memory support, it can be ported Linux operating system
has a compatible IEEE 754-2008 standard FPU
has a branch prediction function, with BTB (Branch Prediction Buff), BHT (Branch History Table), RAS (Return Address Stack)

Superscalar processor out of order --BOOM

BOOM (Berkeley Out-of-Order Machine) is a 64-bit superscalar design UCB, advantages order execution processor, support RV64G, is used to prepare Chisel, Chisel use of only 9000 lines of code, the pipeline may be divided six stages: fetch, decode / rename / allocation instruction, transmit / read register, execution, memory access and write back.

By means Chisel, BOOM is parameterizable superscalar processor configuration, the configurable parameters comprising:

Fetch, decode, submit, instruction issue width
reorder buffer ROB (Re-Order Buffer), the size of the physical register of
the instruction fetch cache, RAS, BTB, load, store queue depth
ordered or unordered emission transmitting
L1 cache the large ones
size MSHRs (Miss Status Handling Registers) of
whether to enable L2 Cache

Processor Family --SHAKTI

SHAKTI [4] is a program of Indian Institute of Technology, the goal is to design a range for different application environments based on open source RISC-V processors, as well as some of the IP core, in order to build SoC. These processors are E-Class, C-Class, I-Class, M-Class, S-Class, H-Class, T-Class, N-Class, now open to the first three, written using Bluespec System Verilog

Embedded applications processor --ORCA

32 is a PicoRV32 VectorBlox designed by the scalar processor, embedded field applied to the target, prepared using VHDL, realized RV32IM, wherein M may be removed extension, extension for multiplication and division is removed, thereby reducing chip footprint, or even remove the timer-related instructions, so that only achieve RV32E

Other open-source processor

(1) RI5CY

RI5CY by the Federal Institute of Technology in Zurich and the University of Bologna joint design of a compact 4-stage pipeline open source processor to achieve a RV32IC, and multiply instructions RV32M in mul, whose goal is to as ultra-low power parallel processor project PULP (Parallel Ultra Low Power) processor core, so RI5CY on the basis of RISC-V based on the increased number of extensions, including hardware cycle multiply-accumulate, and other high-level arithmetic instructions. UMC is using 65nm process flow sheet, RI5CY frequency can reach 654MHz, dynamic power is 17.5uW / MHz [6]. Using SystemVerilog compilation.

(2) RIDECORE

RIDECORE (RIsc-v Dynamic Execution CORE) is out of order by the Tokyo Institute of Technology superscalar processor design release, achieved RV32IM, 6-stage pipeline, namely fetch, decode, instruction dispatch, emission is performed, submit, two instructions can be taken at the same time, to decode two instructions, two instructions submitted. It uses Gshare branch prediction mechanism.

(3) extension

Hwacha by UCB is the development of a vector processor, the UCB Hwacha as a non-standard extension Xhwacha RISC-V have been taped to 28nm and 45nm process repeatedly, the frequency of 1.5GHz or more is still in development , OpenCL compiler is being modified to suit Hwacha, UCB plans to release its code as open source.

(4) f32c

f32c is designed by the University of Zagreb released 32-bit, 5-stage pipeline, a scalar processor, the original MIPS instruction set is implemented, then added to achieve a RISC-V instruction set, branch prediction processor includes direct mapped cache, also announced SDRAM controller, SRAM controller, video FrameBuffer, SPI controller, UART, GPIO and other IP, using VHDL code. Use f32c processor cores, University of Zagreb issued FPGArduino project, which will become a single FPGA development board Arduino board, and can be programmed using the Arduino IDE compiler download.

(5) Z-stairs / V-stairs

Z-scale release of UCB is 32, three lines for embedded environments, transmit single scalar processor, implements RV32IM, the instruction bus and data bus are AHB-Lite. Chisel Z-scale coding is employed, the use of the code Rocket, an increase of only 604 lines of code implement the Z-scale. Verilog is a V-scale version of the corresponding Z-scale.

(6) put

UCB sodor is released for a 32-bit processor family open teaching, using Chisel Coding, you can easily give the corresponding C ++ simulator. There are five sodor series processors, each processor is a single-cycle, two-stage pipelined processor, 3-stage pipeline processors, the pipeline processor 5, the processor may perform microcode.

（7）PicoRV32

PicoRV32 by RISC-V design developer Clifford Wolf release of a size optimized open source processor to achieve a RV32IMC, and can be configured to achieve RV32E, RV32I, RV32IC, RV32IM, RV32IMC depending on the environment. An optional built-in interrupt controller. It features a compact, taking up a LUT 750-2000 on Xilinx7 series chip, speeds of up to 250-400MHz. PicoRV32 using Verilog code.

（8）Tom Thumb

Tom Thumb is a RISC-V design maikmerten developers released a 32-bit, six lines open source processor to achieve the RV32I, the goal is to minimize the footprint of the FPGA, occupies approximately 1200 LEs resources in Cyclone IV series FPGA. Using VHDL code.

（9）FlexPRET

FlexPRET [7] was designed by UCB issued five lines, multi-threaded processor, the goal is to use real-time embedded applications, the number of threads can be configured to 1-8. To improve resource utilization embedded processors, each hardware thread is marked as a hard real-time (hard real-time thread) or soft real-time (soft real-time thread), hard real-time thread is scheduled according to a fixed frequency, if the current no hard real-time threads can be scheduled before scheduling soft real-time thread. Use Chisel write code.

（10）YARVI

YARVI (Yet Another RISC-V Implementation) is a RISC-V design developer Tommy Thorn released a simple, open source 32-bit processors to achieve RV32I, using Verilog as a development language. Its starting point is not the performance, but to be able to clear and accurate implementation RV32I.

Open source SOC

Rocket-Chip

UCB To facilitate learning, but also to facilitate the reuse of already designed hardware module, Rocket-Chip Generator established on GitHub project, which includes a series of bus unit Chisel, GCC, Rocket processor, and the surrounding Rocket , peripherals, caching, and the use of configuration parameters, which can easily create different performance requirements based Rocket processor SoC. Prepared using Chisel, following main sub-modules.

Chisel: open source hardware programming language designed for UCB.
Hardfloat: configurable parameters, compatible with the standard IEEE 754-2008 floating point unit.
Riscv-tools: development tools, including GCC, Newlib, and Linux migration.
Rocket: Rocket processor including L1 Cache.
Uncore: the functional units required to achieve a tight connection to the Rocket, such as L2 Cache, L1 Coherence Hub like.
Juntions: implements the interface conversion between different protocols.
Rocketchip: top module, but also to achieve conversion TileLink internal bus to the external bus of the AHB or AXI.
BOOM introduced hereinbefore, Z-scale can be obtained by configuring the different parameters Rocket-Chip.

LowRISC

LowRISC is a non-profit organization dominated by Cambridge University set up a number of R & D personnel, primarily designed to release 64-bit RISC-V-based SoC Open Source instruction set, whose members have co-raspberry pie, so its goal is to be SoC design made similar raspberry Pi as cheap, feature-rich, with a large number of users of open-source hardware. SoC released the name of LowRISC also LowRISC, Rocket-Chip is based on the development of improved, improving code written using System Verilog part. The main features are:

(1) Tagged Memory: to each memory location have increased a the Tag, the current double word (64bit) corresponding to a Tag (4bit), in order to prevent the flow of control hijacking, but also has other uses, such as: garbage collection set watchpoint and so on. To achieve Tagged Memory, LowRISC RISC-V is increased to two instructions read Tag. April 2015 release of version 0.1 has this feature.

(2) Untethered: Early Rocket-Chip need to rely on the assistance of a general-purpose processor to be able to start to be able to access the serial port, Ethernet port, SD cards and other peripherals, by implementing the Untethered LowRISC (Memory mapping I / O), sheet NASTI interconnect and other functions, to solve the above problems. Version of the November 2015 release of 0.2 has this feature.

(3) Trace Debugging: introduces Open SoC Debug, support Trace Debugging, gather instruction can perform the recording, to facilitate off-line or on-line analysis. July 2016 version 0.3 release has this functionality.

PULPino

PULPino Zurich Federal Institute of Technology and the University of Bologna jointly issued based on RISC-V open-source processor cores RI5CY has been previously described in the Zurich Federal Institute of Technology and the University of Bologna original design of the project is PULP this is a multi-core SoC project, taking into account the project is too complex, there are many IP, custom tools, open source is not convenient, so the developers decided to open a single-core SoC project, PULPino. PULPino direct use many IP PULP projects.

PULPino having a AXI interconnect bus, in addition to an APB bus connecting the low-speed peripherals, such as: GPIO, UART, I2C controller, SPI Master controller. Debug module supports the Advanced Debug Unit. PULPino includes a Boot ROM, which can be written BootLoader, enabling to read the program from the external Flash and executed on startup.

RISC-V VHDL

RISC-V VHDL is Russia's GNSS Sensor-based Rocket has released open-source SoC, its predecessor is a project of the Moscow Institute of Physics and Technology. Processor core of the project directly using a Rocket, can be configured to only L1Cache, can also be configured to include L2Cache, on this basis, it provides a large number of IP cores used in a manner similar LEON3 of GRLIB library, all of the IP nuclear is plug and play, RISC-V VHDL provides an AXI bus, IP core are mounted on the bus. IP core include: UART, GPIO, interrupt controller, Ethernet controller, in addition to support DSU (Debug Support Unit), are used VHDL code.

Most RISC-V VHDL IP core is open source, is the only commercial GNSSLIB, which is a navigation and positioning related to the library, also RISC-V VHDL features.

Some information about RiscV finishing