I. Overview
PULPino is a schema to RISCV RI5CY / ZERO-RISCY kernel mononuclear the SoC, multiplexed with a plurality of components PULP. PULP use of independent single-port data RAM and instruction RAM. It also includes a boot ROM, there are boot loader, an SPI from peripheral flash loader,
Figure 1.1 shows a block diagram of the SoC. PULPino used as the main AXI interconnected with the APB bridge, for simple connection of peripherals. AXI APB and have 32-bit data path. In debug requirements, SoC advanced debug unit comprises a direct access to kernel registers with JTAG, two RAM and memory mapped IO. AXI RAM and two are connected via a bus adapter.
PULPino is a schema to RISCV RI5CY / ZERO-RISCY kernel mononuclear the SoC, multiplexed with a plurality of components PULP. PULP use of independent single-port data RAM and instruction RAM. It also includes a boot ROM, there are boot loader, an SPI from peripheral flash loader,
Figure 1.1 shows a block diagram of the SoC. PULPino used as the main AXI interconnected with the APB bridge, for simple connection of peripherals. AXI APB and have 32-bit data path. In debug requirements, SoC advanced debug unit comprises a direct access to kernel registers with JTAG, two RAM and memory mapped IO. AXI RAM and two are connected via a bus adapter.
Although there are PULPino FPGA version, but its mainly for RTL simulation and ASIC. FPGA version is not particularly optimized in terms of performance, because we mainly use it as a platform rather than independent simulation platform.
Second, the memory map
of FIG. 2.1 shows the hypothetical data and instructions in RAM PULPino are 32kB default memory map. This can be changed in PULPino top SystemVerilog file.
2.1 interrupt vector table
interrupt PULPino follow the definitions RI5CY core vector table.
Like interrupt vector table entry must be a 32-bit, or one or two 16-bit instructions that tell how core processing interrupts. In most cases, this means that the core will jump to the actual execution of the interrupt handler.
Three, CPU core
PULPino support RISCV RI5CY and RISCV ZERO-RISCY two kinds of kernels. Two cores having the same external interface, so you can be plug compatible. Figure 3.1 shows two 3.2 kernel architecture.
of FIG. 2.1 shows the hypothetical data and instructions in RAM PULPino are 32kB default memory map. This can be changed in PULPino top SystemVerilog file.
2.1 interrupt vector table
interrupt PULPino follow the definitions RI5CY core vector table.
Like interrupt vector table entry must be a 32-bit, or one or two 16-bit instructions that tell how core processing interrupts. In most cases, this means that the core will jump to the actual execution of the interrupt handler.
Three, CPU core
PULPino support RISCV RI5CY and RISCV ZERO-RISCY two kinds of kernels. Two cores having the same external interface, so you can be plug compatible. Figure 3.1 shows two 3.2 kernel architecture.
内核使用十分简单的数据和指令接口与数据指令存储器进行通信。为了与AXI通信，在PULPino中实例化了core2axi协议转换器。
处于调试的目的，所有的内核寄存器都已经进行了内存以你干涉，允许通过AXI访问。内核中的调试单元通过总线、读取/设置内核寄存器、halts内核来处理请求。内核支持性能计数器。性能计数器主要用于计算内核内部事件，如停顿，也可以计算内核外部事件。因此，在ext_perf_counters_i端口可以附加任意事件。每次端口有高电平到来时，内核都会增加此事件类型对应的内部性能计数器。
四、advanced debug unit
advanced debug unit包含一个AXI主机接口用于访问外设和存储器。PULPinoV1的advanced debug unit不具有专门的用于读取内核寄存器的接口
所有的内核寄存器都进行了内存映射，这意味着他们都可以通过AXI总线被读取。因此进行可以通过JTAG进行调试，还可以通过SPI或者任何其他接口进行调试。
JTAG信号被连接到SoC的引脚上。
advanced debug unit包含一个AXI主机接口用于访问外设和存储器。PULPinoV1的advanced debug unit不具有专门的用于读取内核寄存器的接口
所有的内核寄存器都进行了内存映射，这意味着他们都可以通过AXI总线被读取。因此进行可以通过JTAG进行调试，还可以通过SPI或者任何其他接口进行调试。
JTAG信号被连接到SoC的引脚上。
有关调试的相关细节，请查看advanced debug unit的文档
五、外设
PULPino中的所有外设都连接到APB总线，但SPI从设备除外，它是一个十分特殊的设备。有关SPI从设备的相关信息，参考第六节
原文下载：https://github.com/pulp-platform/pulpino/blob/master/doc/datasheet/datasheet.pdf