Table of contents
foreword
I am currently a small graduate student, and I am learning about digital IC front-end design. The purpose of creating this project is to learn RISC-V, hoping to deepen the understanding of digital IC design through the study of this project. There may be mistakes in the code and other aspects, I hope everyone can understand.
Related information reference
- "Computer Composition and Design - Hardware-Software Interface (risc-v)"
- 《Computer Organization and Design RISC-V edition》
- "Teach you how to design CPU-RISC-V processors"
- "RISC-V Architecture and Embedded Development Quick Start"
- 《The RISC-V Instruction Set Manual Volume I: Unprivileged ISA》
- "RISC-V Instruction Set Handbook Volume 1: User-Level Instruction Set Architecture (User-Level ISA) Version 2.1"
- 《The RISC-V Instruction Set Manual Volume II: Privileged Architecture》
- "RISC-V Instruction Set Manual Volume 2: Privileged Architecture (Privileged Architecture) Privileged Architecture Version 1.7"
- "The RISC-V Reader Chinese Edition"
- 《riscv-debug-spec-stable_0.13》
- 《riscv-debug-release_0.13.2》
- "Introduction to Homemade CPU"
- "Handwriting CPU"
- Hummingbird e203 open source risc-v
Deilt_RISC Introduction
Project address: Please refer to DEILT_RISCV
design documents (record design process, ideas, and problem solving, etc.): ./Arch/DEILT_RISC_SPEC.md
1 feature
This project plans to design a five-stage pipelined single-core 32-bit processor (Deilt_RISCV), written in Verilog. It has the following characteristics:
- working frequency()?
- Five-stage pipeline with in-order issue and in-order write-back execution
- Single cycle and multiple cycles?
- Static Forecasting Mechanism
- RV32I (40 instructions) (32-bit general-purpose registers, basic integer instruction set)
- Extended instruction M, multiplication and division expansion (4 multiplication, 2 division, 2 remainder), and trial business method to realize division operation
- Only supports machine mode (Machine Mode)
- ITCM and DTCM (Sram)?
- Verilog 2001 grammar writing
- Support outages?
- The interface between the module and the module adopts strict valid-ready handshake interface
- IP modules include: interrupt controller, timer (TImer), UART, SPI
- Support JTAG debugging?
- To be continued. . .
2 Architecture
3 Description of project directory files
Deilt_RISC
├─ Arch
├─ book
├─ DC
├─ isa
│ └─ rom_addi_inst_test.txt //简单的指令测试文件
├─ libs
├─ rtl
│ ├─ core //riscv_core
│ │ ├─ ex.v //执行模块
│ │ ├─ ex_mem.v //ex_mem模块
│ │ ├─ id.v //译码模块
│ │ ├─ id_ex.v
│ │ ├─ if_id.v
│ │ ├─ mem.v //访存模块
│ │ ├─ mem_wb.v
│ │ ├─ pc.v //program counter
│ │ ├─ ram.v //存储器
│ │ ├─ regfile.v //32位通用寄存器
│ │ ├─ riscv_core.v //core
│ │ ├─ rom.v //rom，用于存储指令
│ │ └─ wb.v //写回模块
│ ├─ debug
│ ├─ defines //定义文件夹
│ │ └─ defines.v
│ ├─ general
│ │ ├─ gnrl_dffs.v //通用D触发器
| | | ├─ gnrl_dfflrd //with Load-enable and Reset, Default reset value is default_vlu
| | | ├─ gnrl_dfflrs //with Load-enable and Reset, Default reset value is 1
| | | ├─ gnrl_dfflr //with Load-enable and Reset, Default reset value is 0
| | | ├─ gnrl_dffl //with Load-enable, no reset
| | | ├─ gnrl_dffrs //with Reset, no load-enable ,Default reset value is 1
| | | ├─ gnrl_dffr //with Reset, no load-enable, Default reset value is 0
| | | ├─ gnrl_latch //general latch
│ │ ├─ gnrl_ram.v //通用SRAM
│ │ ├─ gnrl_ram_2clock.v
│ │ └─ gnrl_xchecker.v //不定态检测模块
│ ├─ perips
│ └─ soc
├─ sdk
├─ sim
├─ tb
│ ├─ 20230310tb_for_i.v
│ └─ core_tb(addi).v //2023-3-13简单测试add的tb模块
├─ tools
├─ LICENSE
├─ README.md
└─ tree.tree
4 Simulation compilation environment and tools
-
system
-
CentOS Linux release 7.9.2009 (Core)
-
Linux version 3.10.0-1160.53.1.el7.x86_64
-
-
GNU
- gcc version 4.8.5 20150623 (Red Hat 4.8.5-44) (GCC)
- riscv32-unknown-elf-gcc (g) 11.1.0
- GUN Make 4.2
-
verilog compilation simulation
- Compiler version = VCS-MX O-2018.09-1
- Release Verdi_O-2018.09-SP2 for (RH Linux x86_64/64bit)
-
Other tools
- VIM - Vi IMproved 8.2 (2019 Dec 12, compiled May 21 2022 19:29:38)
- TCL 8.5.13
process
2023/03/01
- Learned the basics
- built the basic structure
- Initially determined the implementation functions and requirements of deilt_risc
- Initially wrote the design draft of deilt_risc
- The next step is to design the data path and realize Deilt_Risc from zero to one
2023/03/08-03/13
- Build a data path for I-type instructions
- Complete the design of the relevant code
- Complete ADD-related i-type instruction verification
- Write design-related documents
2023/03/13-2023/03/15
- Added pipeline hazard cases and solutions to documentation (DEILT_RISCV_SPEC) (03/14)
- Complete the function of rtl code to deal with pipeline adventure
- Write simple pipeline test instructions for testing
- Completing the simulation test through pipeline adventure compilation
2023/03/15-2023/03/16
- Added R-type instruction related part in rtl
- Completed the compilation and simulation of R-type instructions
- Added a description of the R-type instruction in the design document
2023/03/16-2023/03/23
- Pipeline pauses and branch prediction are explained in the documentation
- Modify the pipeline data path diagram, add CTRL and PRDCT modules
- Modify the rtl code, add CREL module and PRDCT module
- Added a branch jump instruction to the instruction
- The U-shaped command was added to the command
- debug
- Completed the simulation test of I, R, U, J, B type instructions, all passed
2023/03/23-2023/03/25
- Implement LOAD, STORE instructions
- Added pause pipeline for ID modules
- All the above instructions have completed the compilation simulation test