Clock distribution of JESD204 IP core (ultrascale series)

Clock distribution of ultrascale series FPGA

JESD204 requires 5 clocks, namely:

1. The clock refclk of the transceiver,

2. The core clock core_clk, the core clock rate is 1/40 of the transmission rate of a single lane,

3. AXI bus clock s_axi_aclk,

4. Dynamic configuration clock drpclk,

5. Deterministic delay sysref, the clock and core_clk must have the same source. The sysref rate is: Lane_rate/(10*F*K)/2^N; N is a positive integer.

         The clock network can be allocated according to the clock network diagram below. After passing through IBUFDS_GT, refclk is divided into two paths, one path is sent to the transceiver, and the other path is sent to the core clock through BUFG_GT. The clock after BUFG_GT can be used as the user clock. You can use this clock frequency division to get sysref.

        There are no specific requirements for s_axi_aclk and drpclk, and can be obtained by frequency division of the FPGA clock, or by frequency division of the core clock.

Concrete implementations are implemented by primitives.

//时钟分配

    IBUFDS_GTE3 CPLL_CLK (
        .I      (refclk_p               )   ,
        .IB     (refclk_n               )   ,
        .CEB    (1'b0                   )   ,
        .O      (refclk                 )   ,  //作为收发器的时钟
        .ODIV2  (refclk_1               )      //经过BUFG_GT后作为/core_clk
    );

    BUFG_GT refclk_bufg_gt_i  (
        .I       (refclk_1      )   ,
        .CE      (1'b1          )   ,
        .CEMASK  (1'b0          )   ,
        .CLR     (1'b0          )   ,
        .CLRMASK (1'b0          )   ,
        .DIV     (3'b000        )   ,
        .O       (refclk_2      )       //core_clk
    );

    refclk_wiz  u_refclk_wiz(
        .clk_160    (core_clk       )   ,     // output clk_160
        .clk_100    (clk_100_ref    )   ,     // output clk_100
        .reset      (reset          )   , // input reset
        .locked     (locked_ref     )   ,       // output locked
        .clk_in1    (refclk_2       )        //input  160MHz
    );      // input clk_in1 

After BUFG_GT, the clock can be divided by the IP core to get the clock we need.

Ultrascale series FPGA: location selection of GTH

       For the ultrascale series to configure JESD204 PHY , you need to select the location of the transceiver. You can check it through the IP core of UltraScale FPGAs Transceivers Wizard, look at the channel of physical resources, check the BANK corresponding to the transceiver, and select the location of the transceiver through the BANK of the schematic diagram.

For GTH, four transceivers constitute a Qaud, and there are four CPLLs, a QPLL1, and a QPLL0 in a Qaud.