illustrate
Due to an issue in Intel® Quartus® Prime Professional Edition software 23.4 and earlier, static timing constraints for the *c2p_fa_div_clk_** clock within the Intel Agilex® 5 LVDS SERDES IP may not be generated correctly.
This issue occurs when the Intel Agilex® 5 LVDS SERDES IP is configured with more than 4 bytes in RX DPA-FIFO mode or RX soft CDR mode and implements associated TX channels.
Warning (332087): The master clock for this clock assignment cannot be exported. Clock: *|core|arch_inst|c2p_fa_div_clk_** Not created.
Solution
A workaround is required to resolve this issue. In the lvds_intel_lvds_core10_ph2_191_*.sdc files, replace:
intel_lvds_create_generated_clock \
-source [intel_lvds_get_clock_source “$c 2p_fa_gen_clk”] \
-divide_by 2 \
-duty_cycle 50 -阶段 0 \
-name “${lvds_instance_name}|c2p_fa_div_clk_${byte}” -target “${c2p_fa_gen_clk}”
与
设置master_clock “”
set all_clocks [get_clocks -nowarn -of_objects [get_registers $c 2p_fa_gen_clk]]
foreach_in_collection clk $all_clocks {
设置clk_name [get_clock_info -名称$clk]
if {（[string first $lvds_instance_name $clk_name] ！= -1） && （[string first “fclk0” $clk_name] ！= -1）} {
设置 master_clock $clk_name
打破
}
}
intel_lvds_create_generated_clock \
-source [intel_lvds_get_clock_source “$c 2p_fa_gen_clk”] \
-divide_by 2 \
-duty_cycle 50 -阶段 0 \
-name “${lvds_instance_name}|c2p_fa_div_clk_${byte}” -target “${c2p_fa_gen_clk}” \
-master_clock $master_clock
This issue is planned to be fixed in a future release of Intel® Quartus® Prime Professional Edition software.
12/21 Record