Detailed explanation of the basic principles of Σ-Δ ADC topology

The Σ-Δ ADC is an essential and basic device in the toolbox of today's signal acquisition and processing system designers. The purpose of this article is to provide the reader with a basic understanding of the underlying principles behind the Σ-Δ model ADC topology. This article explores examples of trade-off analysis between noise, bandwidth, settling time, and all other critical parameters relevant to ADC subsystem design to provide context for designers of precision data acquisition circuits.

It usually consists of two modules: a Σ-Δ modulator and a digital signal processing module, which is usually a digital filter. A brief block diagram and main concepts of a Σ-Δ ADC are shown in Figure 1.

Figure 1. Key concepts of Σ-Δ ADCs

The Σ-Δ modulator is an oversampling architecture, so we start our discussion with Nyquist sampling theory and scheme and oversampling ADC operation.

Figure 2 compares the ADC’s ​​Nyquist operation, oversampling scheme, and Σ-Δ modulation (also oversampling) scheme.

Figure 2. Nyquist comparison

Figure 2a shows the quantization noise when the ADC is operated in standard Nyquist mode. In this case, the quantization noise is determined by the LSB size of the ADC. FS is the sampling rate of the ADC, and FS/2 is the Nyquist frequency. Figure 2b shows the same converter, but now it is running in an oversampling mode, sampling at a faster rate. The sampling rate is increased by K times, and the quantization noise extends to the bandwidth of K × FS/2. A low-pass digital filter (usually with decimation) removes quantization noise outside the blue area.

Figure 2a. Nyquist scheme. The sampling rate is FS and the Nyquist bandwidth is FS/2

Figure 2b. Oversampling scheme. The sampling rate is K × FS

The Σ-Δ modulator has one more feature, which is noise shaping, as shown in Figure 2c. The quantization noise of analog-to-digital conversion is modulated and shaped, moving from low frequencies to higher frequencies (usually), and a low-pass digital filter removes it from the conversion result. The noise floor of a Σ-Δ ADC is determined by thermal noise and is not limited by quantization noise.

Figure 2c. Σ-Δ ADC scheme. Oversampling and noise shaping, the sampling rate is FMOD = K × FODR

Sampling, modulation, filtering

Σ-Δ ADCs use an internal or external sampling clock. The ADC's master clock (MCLK) is often divided down before being used by the modulator; you should pay attention to this when reading the ADC data sheet, and understand the modulator frequency. The clock passed to the modulator sets the sampling frequency FMOD. The modulator outputs data at this rate to a digital filter, which in turn provides the data at the output data rate (ODR). Figure 3 shows this process.

Figure 3. Σ-Δ ADC flow: sampling from modulator output to digital filtered output

An in-depth look at first-order Σ-Δ modulators

A sigma-delta modulator is a negative feedback system, similar to a closed-loop amplifier. The loop contains the low-resolution ADC and DAC, as well as a loop filter. The output and feedback are roughly quantized, often with only one bit representing a high or low level of the output. The analog system of the ADC implements this basic structure, and the quantizer is the module that completes sampling. If conditions exist that guarantee the stability of the loop, then the output is a rough representation of the input. A digital filter takes this coarse output and reconstructs an accurate digital conversion of the analog input.

Figure 4 shows the 1 density output in response to a sine wave input. The rate at which the modulator output changes from low to high depends on the rate of change of the input. When the sine wave input is at positive full scale, the modulator output switching rate will decrease and the output will be mainly in the +1 state. Likewise, when the sine wave input is negative full scale, the transition between +1 and –1 is reduced and the output is dominated by –1. The highest density of +1 and –1 switching occurs at the modulator output when the sine wave input is at its maximum rate of change. The rate of change of the output is synchronized with the rate of change of the input. Therefore, the analog input is described by the slew rate of the Σ-Δ modulator output.

Figure 4. Density of 1-code values ​​at the Σ-Δ output for an input sine wave. Linear model of the 1st order Σ-Δ modulator loop (a)

If a linear model is used to describe this 1-bit modulator (Mod 1), the system can be expressed as a control system with negative feedback. Quantization noise is the difference between the input and output of the quantizer. The input bias node is followed by a low-pass filter. In Figure 5b, quantization noise is represented by N.

Figure 5. Linear model (b) of the Mod 1 Σ-Δ loop, including equations, filters, signal and noise transfer function plots

H(f) is a function of the loop filter and defines the transfer function of noise and signal. H(f) is a low-pass filter function that has very high gain at low frequencies (within the target bandwidth) and can attenuate high-frequency signals. The loop filter can be implemented as a simple integrator or a cascade of integrators. In practice, a DAC is often placed in the feedback path to obtain the digital output signal and convert it into an analog signal that is fed back to the analog input deviation node.

Solving the equations shown in Figure 5 yields the signal and noise transfer functions. The signal transfer function acts as a low-pass filter with a gain of 1 within the bandwidth of interest. The noise transfer function is a high-pass filter function that provides noise shaping and has strong suppression of quantization noise at lower frequencies near DC. The quantization noise seen at higher frequencies beyond the target bandwidth increases. For a first-order modulator (Mod 1), the noise increases at a rate of approximately 20 dB/decade.

In order to improve the system resolution, a common method is to cascade two loop filters to increase the loop filter order. The total loop filter H(f) now has a larger roll-off, and the Mod 2 noise transfer function has a rise rate of 40 dB/decade. The lower the frequency the noise is at, the more powerful the noise shaping is. Figure 6 compares Mod 1 and Mod 2 Σ-Δ ADCs. There are many variations and styles of sigma-delta modulators. An architecture that circumvents the high-order 1-bit loop stability problem is called a multistage noise-shaping modulator (MASH) architecture. The multi-stage (MASH-type) architecture enables the design of stable high-order Σ-Δ modulators by combining low-order loops with inherent stability.

Figure 6. Comparison of Mod 1 and Mod 2 block diagram configurations and filter and noise transfer functions.