Function description
Cyclone® devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks.
Cyclone® devices contain two-dimensional row and column architectures to implement custom logic. Variable-speed column and row interconnects provide signal interconnections for LABs and embedded memory blocks.
The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. Cyclone devices range between 2,910 to 20,060 LEs.
The logic array consists of LABs with 10 LEs in each LAB. An LE is a small unit of logic that provides an efficient implementation of user logic
functions . LABs are grouped into rows and columns on the device. Cyclone devices range from 2,910 to 20,060 LEs.
M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 250 MHz. These blocks are grouped into columns across the device in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of embedded RAM.
M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual port, simple dual port or up to 36 bit wide single port memory up to 250 MHz. These blocks are grouped on the device and listed between certain LABs. Cyclone devices offer between 60 and 288 Kbits of embedded RAM.
Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the ends of LAB rows and columns around the periphery of the device. I/O pins support various single-ended and differential I/O standards, such as the 66- and 33-MHz, 64- and 32-bit PCI standard and the LVDS I/O standard at up to 640 Mbps. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals. Dual-purpose DQS, DQ, and DM pins along with delay chains (used to phase-align DDR signals) provide interface support with external memory devices such as DDR SDRAM, and FCRAM devices at up to 133 MHz (266 Mbps).
Each Cyclone device I/O pin is fed by the I/O Element (IOE) located at that location, feeding the end of the row and column of LABs on the periphery of the device. The I/O pins support various single-ended and differential I/O standards such as 66 and 33 MHz, 64 and 32-bit PCI standard LVDS I/O standard up to 640 Mbps. Each IOE contains a bidirectional I/O buffer and three register signals for registering input, output, and output enable. Dual-channel DQS, DQ and DM pins and delay chains (for aligning DDR signals) provide an interface to support external memory devices such as DDR SDRAM and FCRAM devices up to 133 MHz (266 Mbps).
Cyclone devices provide a global clock network and up to two PLLs. The global clock network consists of eight global clock lines that drive throughout the entire device. The global clock network can provide clocks for all resources within the device, such as IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals. Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O support.
Cyclone devices provide a global clock network and up to two PLLs. This global clock network is driven across the device by eight global clock lines. A global clock network can provide clocks to all resources within the device, such as IOEs, LEs, and memory blocks. Global clock lines can also be used for control signals. The PLL provides general-purpose clocking with clock multiplication and phase shifting and external output support for high-speed differential I/O.
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect, look-up table (LUT) chain, and register chain connection lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE's LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE's register to the adjacent LE's register within a LAB. The Quartus
®
II Compiler places associated logic within a LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency.
Figure 2–2
details the Cyclone LAB.
Each LAB consists of 10 LEs, LEs carry chains, LAB control signals, a local interconnect, look-up table (LUT) chain and register chain connection lines. Local interconnects carry signals between LEs within a LAB. A LUT chain connection transfers the output of one LE's LUT to an adjacent LE for fast-continuous LUT connection within the same LAB. A register chain connection transfers the output of a register of one LE to a register of an adjacent LE within the LAB. The Quartus® II Compiler places related logic within a LAB or adjacent LABs, allowing the use of local, LUT chains, and registered chain connections for performance and area efficiency. Figure 2-2 details the Cyclone LAB.
Interconnection of LAB blocks:
The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM blocks from the left and right can also drive a LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 30 other LEs through fast local and direct link interconnects. Figure 2–3 shows the direct link connection.
LAB local interconnects can drive LEs within the same LAB. LAB local interconnects are driven by column and row interconnects and LE outputs. Adjacent LABs, PLLs and blocks to the left and right of the M4K RAM can also drive the local interconnects of the LABs
via direct link connections. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can quickly drive up to 30 other LEs local and direct link interconnects. Connect as shown in Figure 2-3.
LAB control signals:
Each LAB contains dedicated logic for driving control signals to its LEs.The control signals include two clocks, two clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, synchronous load, and add/subtract control signals. This gives a maximum of 10 control signals at a time. Although synchronous load and
clear signals are generally used when implementing counters, they can also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB's clock and clock enable signals are linked. For example, any LE in a particular LAB using th
labclk1
signal will also use
labclkena1
. If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals. Deasserting the clock enable signal will turn off the LAB-wide clock
Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous load acts as a preset when the asynchronous load data input is tied high.
Each LAB contains dedicated logic for driving control signals to its LEs. Control signals include two clocks, two clock enables, two asynchronous clears, synchronous clears, asynchronous preset/load, synchronous load and add/subtract control signals. This gives up to 10 control signals at a time. While synchronizing loads and they can be commonly used when implementing counters, clear signals can also be used with other functions.
Each LAB can use two clocks and two clock enable signals. The clock and clock enable signals for each LAB are linked. For example, any specific LAB whose LE uses the labclk1 signal will also use labclkena1. If a LAB uses the rising and falling edges of the clock, it also uses both LAB-wide clock signals. Removing the divided clock enable signal will turn off the LAB wide clock
Each LAB can use two asynchronous clear signals and asynchronous signal load/preset signals. Asynchronous load as the default value when the asynchronous load data input is pulled high.
With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder and subtractor. This saves LE resources and improves performance for logic functions such as DSP correlators and signed multipliers that alternate between addition and subtraction depending on data.
Using the LAB-wide addnsub control signal, a single LE can implement a one-bit adder and subtractor. This saves LE resources and improves the performance of logic functions such as DSP correlators and signature multipliers that alternate between addition and subtraction depending on the data.
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide control signals. The MultiTrackTM interconnect's inherent low skew allows clock and control signal distribution in addition to data. Figure 2–4 shows the LAB control signal generation circuit.
LAB row clocks [5..0] and LAB local interconnects generate LAB wide control signals. The inherent low-level skew of the MultiTrackTM interconnect allows clock and control signal distribution in addition to data. The LAB control signal generation circuit is shown in Figure 2-4.
