Struggling Child Series FPGA Learning Altera Series: Chapter Six Design and Simulation Test of Multiplexer
Author: Xu Hao Shuai struggling child (please indicate the source)
Hello heroes, welcome to the FPGA technology arena, the rivers and lakes are huge, meeting is fate. Heroes can pay attention to the FPGA technology arena, get other interested resources in the "Crossing the Rivers and Lakes" and "Xing Xia Zhanyi" column, or cook together.
Today, we bring the "FPGA learning series altera" series to Heroes, which will continue to be updated.
This learning experience is written by me before, the design software used is Quartus II 13.1, the new version of Quartus has been updated to 20+, the following is only for beginners to learn reference. Other series will be updated in the future, so stay tuned. Not much to say, get the goods.
Chapter Six: Design and Simulation Test of the Two-to-One Multiplexer
In digital circuits, the two-to-one multiplexer has the simplicity and classic characteristics of combinational logic circuits. Our first design starts with "it".
The project name is "mux2_1", and the architecture diagram is as follows:
Port description:
Input: a, b, s.
Output: c.
Function description:
When "s" is high level, "c" is equal to "a"; when "s" is low level, "c" is equal to "b";
Verilog code implementation:
/*
模块名称：mux2_1
模块功能：当“s”为高电平时，“c”等于“a”；当“s”为低电平时，“c”等于“b