The basic I FPGA Virtex family / O resources comprise a logical combination of input and output resources, three-state output control, output control register input, input and output the SDR, DDR output tri-state control. Further V5, V6 IODELAY device further comprising providing the user control over the high-resolution adjustable delay unit, the SAME_EDGE DDR output mode, SAME_EDGA SAME_EDGA_PIPELINED input and DDR mode, the following is a summary of the main personal learning record.
An input-output delay unit IODELAY
each I / O module contains a programmable delay unit IODELAY absolute. It can connect to ILOGIC / ISERDES or OLOGIC / OSERDES module. IODELAY tap 64 surrounding units. By selecting IDELAYCTRL reference clock delay resolution may be changed in the 64 tap. IODELAY may be used in combination of input / output paths, register input / output channels, may be used directly in the internal resources.
(1) When used as the IDELAY, data input from the IBUF or internal resources, and then output to ILOGIC / ISERDES.
* Zero hold time mode, where IDELAY_TYPE = Default, this embodiment mode does not require IDELAYCTRL primitive.
* A fixed time delay mode, where IDELAY_TYPE = FIXED, in this mode, the delay time preset values arranged into a number determined by the attribute Tap IDELAY_VALUE. Example IDELAYCTRL primitive must use.
* Variable delay mode, the delay can be changed by the control signal CE and INC is configured, it must be instantiated IDELAY_CTRL use.
(2) which ODELAY, data input from OLOGIC / OSERDES. Tap preset value to a number determined by the configuration ODELAY_VALUE, IDELAYCTRL element must be instantiated when used.
(3) Bidirectional delay among the IOB configured bidirectional mode, The IODELAY alternately output via the input delay. There are following two modes can be equipped
* A fixed time delay mode, where IDELAY_TYPE = FIXED, in this mode, the delay time preset values arranged into a number determined by the attribute Tap IDELAY_VALUE. Example IDELAYCTRL primitive must use.
* Variable delay mode, the delay can be changed by the control signal CE and INC is configured, it must be instantiated IDELAY_CTRL use.
Under normal circumstances, if only example of a IDELAYCTRL, you can not add LOC constraints, but when more than one example of IDELAYCTRL when it is necessary to add location constraints, otherwise ISE software will report an error when the comprehensive implementation.
Second, the use of IDELAYCTR
if IOBDELAY_TYPE property is set to the VARIABLE or FIXED, it must be instantiated in the code module IDELAYCTRL, IDELAYCTRL continuous calibration module delay units in their respective sections, a brief summary of the use of IDELAYCTRl.
(1) No LOC constraint IDELAYCTRL
when IDELAYCTRL when the embodiment of no LOC constraints, HDL code must only embodiment of a IDELAYCTRL example, automatically copied to the delay means clocks the entire area of the device which when ISE implemented, so that each clock region has consumed resources than a global clock, layout resource usage is relatively high, and thus the power consumption of the chip is relatively large.
When RDY port is ignored, so the duplicated signal RDY IDELAYCTRL example not connected, but when the RDY connection port, for example a width equal to all of the AND gates IDELAYCTRL, automatically connects to the embodiment has been implemented based upon the number of clocks ISE region RDY signal gate output port instance.
(2) LOC constraints IDELAYCTRL
use IDELAYCTRL module most effective way is to define and position tags embodiment of all IDELAYCTRL instances lock, the Xilinx officially recommended when using the delay unit should be defined and lock all ISERDES and IDELAY element location, use LOC constraints have IDELAYCTRL
LOC is added IDELAYCTRL Note:
a IDELAYCTRL primitive can cover a clock region, and a clock region contains more than one IOB, when IDELAYCTRL primitive constraint LOC, LOC which requires careful positioning of the IOB IDELAYCTRL belongs.
(3) location constraint
each module has a IDELAYCTRL XY coordinate position for the restraint position, IDELAYCTRL instances can have LOC properties, may be added INST "Instance name" LOC = IDELAYCTRL_X # Y # is attached IDELAYCTRL LOC UCF file attributes; or LOC directly embedded in the HDL design constraint file
The following syntax for embedding LOC constraints in the HDL design file.
// synthesis attribute loc of instance_name is " IDELAYCTRL_X # Y #";
such as a complete example:
The IODELAY # (
.DELAY_SRC ( "O"), // The IODELAY source is ODATAIN
.IDELAY_TYPE ( "FIXED"), // static delay
.ODELAY_VALUE (16), // number of fixed delay 16 TAP
.REFCLK_FREQUENCY (200.0) // the IDELAYCTRL reference clock 200MHz
) IODELAY_INST
(
.C (1'b0), the clock input of the variable mode //
. CE ( 1'b0), // whether to enable increment / decrement function
.DATAIN (1'b0),
.IDATAIN (1'b0),
.INC (1'b0), // TAP delay of up / down to select
.ODATAIN (LED ), // from OLOGIC / OSERDES signal
.rst (1'b0),
.T (1'b0), // used ODELAY
.DATAOUT (the LED)
);
the IDELAYCTRL IDELAYCTRL_inst
(
.rdy (the RDY), //. 1 -bit ready output
.REFCLK ( System_Clk ), // 1-bit reference clock input
.RST ( 1'b0 ) // 1-bit reset input
);
Third, Advanced SelectIO Logic Resources (ChipSync)
Advanced SelectIO ISERDES and logic resources including the OSERDES, it can support a very high I / O data rate, allowing the internal logic at a rate of less than I / O operation. BitSlip sub-module, re-alignment of the training mode according to the detection data.
(1) ISERDES function
dedicated deserializer / deserializer: ISERDES high speed data transmission can be achieved, completely without internal logic of FPGA frequency matching with the input data, this converter supports SDR, DDR mode. In SDR mode, the serial to parallel converter may create 2,3,4,5,6,7,8-bit wide parallel words in DDR mode deserializer create 4,6,8,10-bit wide parallel word.
BitSilp sub-module: This module into the FPGA fabric support parallel data reordering function can be used to synchronize the training pattern of the source port.
(2) A method to expand ISERDES width
of each I / O module has a master-slave ISERDES two modules, for constructing greater than 1: need in cascade connecting two serial converter 6 ISERDES. SHIFOUT port connection to the main ISERDES ISERDES SHIFIN port, the serial to parallel converter may be extended to a maximum of 1:10 (DDR mode), and 1: 8 (SDR mode). Guidelines for extending bit-wide parallel converter follows:
A, ISERDES two adjacent main modules must be from the right.
B, and the main set of ISERDES SERDES_MODE MASTER, from the ISERDES SERDES_MOD to Slaver.
C, the port connected to the Slave shifin shifout the master port.
D, Slave using only the port as an input port Q3 ~ Q6.
Equal to the data width E, Master and the Slave.
(. 3) OSERDES modules
each module comprising a OSERDES data for a specific conversion and a three-state controlled. And tri-state data can be configured as SDR and DDR mode, the serial data of up to 6: 1, if the width of the expansion, it can reach 10: 1, three serial ports of up to 4: 1.
Extension method (4) OSERDES module: consistent expansion and Iserdes Oserdes extended mode.