1.2.16. Some advanced features of Nand Flash
1.2.16.1. Nand Flash的Unique ID
1.2.16.1.1. What is Unique ID?
Unique ID, translated into Chinese is a unique ID, unique identification.
Obviously, this Unique ID is used to identify something, and each thing has a unique identification information.
The Unique ID in Nand Flash is mainly a certain ID information to ensure that each Nand Flash is unique. It is mainly used by other users who use Nand Flash to do encryption and other applications according to this unique id to realize certain security applications.
In short, it is to use Nand Flash's Unique ID to implement security-related applications, such as encryption, copyright protection, and so on.
1.2.16.1.2. Different Nand Flash vendors' different implementation methods for Unique ID
Here, before continuing to explain, I will repeat it again:
Currently, the manufacturers of Nand Flash include Samsung, Toshiba, Intel, Hynix, Micron, Numonyx, Phison, SanDisk, Sony, Spansion, etc.
Due to the aforementioned Nand Flash specification dispute, that is, the dispute between Toshiba & Samsung and Intel + other vendors (Hynix, Micron, Numonyx, Phison, SanDisk, Sony, Spansion, etc.), this has led to such a small feature point for Unique ID (Feature), different aspects have come up with different implementations (practices).
Here is an explanation of how each manufacturer implements Unique ID and how to read the corresponding Unique ID:
1.2.16.1.2.1. Unique ID of Toshiba's Nand
Find a datasheet online:
Toshiba TH58NS512DC
http://datasheet.elcodis.com/pdf/11/23/112371/th58ns512dc-to51y.pdf
Mentioned in:
P1: "The TH58NS512DC is a SmartMediaTM with ID and each device has 128 bit unique ID number embedded in the device. This unique ID number is applicable to image files, music files, electronic books, and so on where copyright protection is required." That is, each Toshiba's TH58NS512DC has a Unique ID of 128 bit=16 byte, which can be used for copyright protection in applications such as pictures, music, and e-books.
P24:
Figure 1.9. Toshiba's Unique ID
1.2.16.1.2.2. Read Toshiba's Nand Unique ID
As can be seen from the above, in Toshiba's Nand, with regard to Unique ID, it is necessary to read the Nand ID first through the ordinary 0x90, that is, the Read ID command, find the third byte (3rd byte), and then judge it. Whether it is 0xA5, if it is 0xA5, then it can be determined that there is a Unique ID in this Nand, and then it is said that the Unique ID is read.
As for how to lack Unique ID, you need to contact Toshiba with yourself and sign an NDA agreement with it before you can learn how to read Nand's Unique ID.
1.2.16.1.3. Samsung Samsung’s Nand Unique ID
A datasheet of Samsung’s Nand found on the Internet:
Samsung K9F5608U0B
http://hitmen.c02.at/files/docs/psp/ds_k9f5608u0b_rev13.pdf
“
6. Unique ID for Copyright Protection is available
- The device includes one block sized OTP (One Time Programmable), which can be used to increase system security or to provide identification capabilities. Detailed information can be obtained by contact with Samsung
”
That is, Samsung's Nand's Unique ID is also similar in purpose to Toshiba, and is mainly used for copyright protection, but its implementation is different.
The realization of Samsung's Unique ID is specially equipped with an OTP block in Nand, and the block size of this Nand chip is 16KB.
Regarding how to operate this OTP, that is, how to write data and read data, it is not explained here.
For details, please contact Samsung.
However, I understand that it should be similar to the operation of ordinary blocks, that is, ordinary blocks contain many pages. Each page operation has a corresponding page read. Use the corresponding page read command to read this special OTP block. The data.
And what the data in this OTP block is depends entirely on what data you write into it at the beginning. To put it bluntly, according to your own needs, when your product leaves the factory, write the corresponding data, such as the SN serial number of the product, and then use page read to read the corresponding data and analyze it yourself. Get the information you want and use it for your own purposes, such as copyright protection.
1.2.16.1.3.1. Read Samsung's Nand Unique ID
As mentioned earlier:
Regarding how to operate this OTP block, that is, how to write data and read data, it is not explained here.
That is, if you want to know how to read Samsung's Nand Unique ID, please ask Samsung yourself.
1.2.16.1.4. Nand's Unique ID of manufacturers that follow ONFI specifications
Mainly refers to Intel, Hynix, Micron, Numonyx, Spansion and other companies.
The related definitions of the corresponding Nand's Unique ID are included in ONFI's specifications, and are briefly excerpted as follows:
ONFI 2.2
http://onfi.org/wp-content/uploads/2009/02/ONFI%202_2%20Gold.pdf
In the ONFI specification, in "5.7.1. Parameter Page Data Structure Definition", as shown in the figure:
Figure 1.10. ONFI's parameter page data structure definition
Defines the data of a page, which is used to store various parameters of the corresponding Nand. Among them, when the 8th byte bit5==1, it indicates that the command of "Read Unique ID" is supported, which means this Nand chip This command is supported. If bit5==0 of byte8, it means that it is not supported and it is impossible to read Unique ID.
1.2.16.1.4.1. Read the Nand Unique ID of the manufacturer that follows ONFI
If after the above judgment, this ONFI-compliant Nand Flash supports the Read Unique ID command, you can use this command to read the unique ID of the corresponding Nand Flash.
The detailed explanation of this Read Unique ID is:
“ 5.8. Read Unique ID Definition
The Read Unique ID function is used to retrieve the 16 byte unique ID (UID) for the device. The unique ID when combined with the device manufacturer shall be unique.
The UID data may be stored within the Flash array. To allow the host to determine if the UID is without bit errors, the UID is returned with its complement, as shown in Table 47. If the XOR of the UID and its bit-wise complement is all ones, then the UID is valid.
”
That is, the Read Unique ID command is used to read the 128bit=16 byte Unique ID, but in order to prevent the written Unique ID from being wrong, a corresponding complement is added after the 16 bytes, that is, each The result of bit inversion, so that the complement of the unique ID of the first 16 bytes and the unique ID of the last 16 bytes form 32 bytes, which are counted as a group, as shown in the following figure:
Figure 1.11. Structure of Unique ID in ONFI
“
To accommodate robust retrieval of the UID in the case of bit errors, sixteen copies of the UID and the corresponding complement shall be stored by the target. For example, reading bytes 32-63 returns to the host another copy of the UID and its complement. Read Status Enhanced shall not be used during execution of the Read Unique ID command
Figure 57 defines the Read Unique ID behavior. The host may use any timing mode supported by the target in order to retrieve the UID data.
”
In order to further prevent errors, the above 32 bytes are counted as one group and repeated 16 times. These 16 32-byte data are stored in Nand Flash, and then read out with the Read Unique ID command to obtain one of them. 32 bytes is enough, and then judge the first 16 bytes and the last 16 bytes to be inverted. If all the bits of the result are 1, then the result is 16 0xFF, then the Unique ID is correct. Otherwise, the description is wrong.
The detailed format of the Read Unique ID command is shown in the figure below:
Figure 1.12. Timing diagram of the Read Unique ID command in ONFI
That is, send the 0xED command first, then send the 0x00 address, and then wait for the busy state of Nand Flash to end, then the 16 groups of 32 bytes can be read out, and then use the above method to judge, find the first 16 bytes and the next The 16-byte XOR result is 0xFF in all 16 bytes, which means that the correct Unique ID is obtained. At this point, the Unique ID that complies with the ONFI specification is read out.
1.2.16.2. CE don't-care technology
Many Nand flashes support a technology called CE don't-care, which literally means that you don't care about chip selection.
Some people may ask about this, if you don't have a film selection, can you still operate it? The answer is that this technology is mainly used in these situations where the chip does not need to be selected at the time, but the chip can still continue to operate: in some applications, such as recording, audio playback and other applications, the external use of microseconds (us) The clock cycle of the level, here is assumed to be a relatively small 2us. When reading a page or programming a page, the Nand Flash operation is performed. The cycle of such serial (Serial Access) access is 20/30/50ns , Are all nanoseconds (ns) level, here is assumed to be 50ns, after you have sent the corresponding read or write command, the next step is to operate inside the Nand Flash to read or write the data Go in to the internal data register. Here, if the chip select can be canceled, CE# is active at low level. To cancel the chip select is to pull the high level, which will be before the next external command is sent, that is, microseconds. Within the level of time, that is, 2us-50ns≈2us, canceling the chip selection during this period can reduce the power consumption of the system very little, but multiple operations can reduce the overall power consumption to a large extent.
In general: because some external applications require a relatively low frequency of accessing Nand Flash, and the internal operation speed of Nand Flash is relatively fast, most of the time for reading or writing to Nand Flash is Waiting for the input of external commands, while selecting the chip at the same time, excess power consumption is generated. This "don't care about chip selection" technology is to cancel the chip selection after the relatively fast operation (read or write) inside the Nand Flash is completed. , In order to save system power consumption. When the next external command/data/address is input, select the chip again to continue the operation normally. In this way, overall, the system power consumption can be greatly reduced.
| prompt | |
|---|---|
|
1.2.16.3. Copy-Back Operation with EDC & Sector Definition for EDC
The Copy-Back function, in simple terms, is to copy the data of one page to another page.
If there is no Copy-Back function, then the normal way is to first copy the data of that page and put it in the data buffer of the memory. After reading it out, use the write command to write the data of this page to a new page. .
The advantage of the Copy-Back function is that it does not need to use external storage space, and does not need to be read to put in an external buffer. Instead, data can be directly read to the internal page register and then written to a new one. Go inside the page.
Moreover, in order to ensure the correctness of the data, the hardware must support EDC (Error Detection Code). Otherwise, errors may occur during the copying of the data, and more errors may accumulate as the number of copies increases.
For error detection, the hardware generally supports 512 bytes of data, corresponding to 16 bytes used to store the ECC value generated by the check, and these 512 bytes are generally called a sector. For a 2K+64-byte page, it is divided into 512 bytes and called areas A, B, C, and D, while the following 64-byte oob area is called E, F, and 16 bytes. The G and H areas correspond to the ECC values stored in the A, B, C, and D data areas.
The main function of Copy-Back programming is to remove the time to read data serially and write it in serially. Therefore, this part of the operation is relatively time-consuming, so this technology can improve programming efficiency and improve the system. Overall performance.
1.2.16.4. Simultaneously Program Multi Plane
For some newly released Nand Flash, it supports programming multiple chips at the same time, such as Samsung’s K9K8G08U0A mentioned above, which contains 4 chips (Plane), called Plane0, Plane1, Plane2, Plane3. Due to the hardware, for each Plane, there is a corresponding page register (Page Register) with a size of 2048+64=2112 bytes, which makes it possible to support multiple Plane programming at the same time. K9K8G08U0A supports programming 2 Planes at the same time.
However, it should be noted that you can only program Plane0 and Plane1 or Plane2 and Plane3 at the same time, and do not support simultaneous programming of Plane0 and Plane2.
1.2.16.5. Interleave Page Program
Simultaneous programming of multiple chips is for multiple Planes in one chip.
The interleaved page programming here refers to multiple chips.
You can program a chip, suppose it is called chip1, and a page inside. Then, at this time, chip1 starts to write data into the page little by little, it is in a busy state, and this time can be used at this time, For chip2 in the ready state, page programming is also performed. After sending the corresponding command, chip2 starts to slowly write data into the memory cell, and it is also in a busy state. At this point, check chip1 again. If the programming is completed, you can start programming on the next page, and then after sending the command, let it program slowly, and then check chip2. If the programming is also completed, also You can proceed with the programming of the next other pages. In this way, the interactive operation of chip1 and chip2 can effectively use time, which increases the overall programming efficiency by nearly 2 times and greatly improves the programming/erasing speed of Nand Flash.
1.2.16.6. Random Data Output In a Page
Before introducing this feature, let me talk about it. The one corresponding to Random Data Output In a Page is normal, normal, sequential data output in a page.
Under normal circumstances, when we read data, we send the read command first, and then wait for the data from the storage unit to the internal page data register. After we continue to set RE# (Read Enale, active low) low, Then read the data we want from the starting address of the column we started to pass in, until the end of the page. Of course, it may not be read until the end of the page address. The so-called sequential reading is that, starting from the starting address of the column address you sent before, every time a byte of data is read, the internal data pointer is incremented by 1, and it moves to the address of the next byte. Then you read the next byte of data, you can read out the data you want, until all the data is read out.
The random read here means that in your normal sequential read process, first send a random read start command 0x05 command, and then pass in the specific address you want to locate the internal data pointer. , Which is the column address of 2 cycles, and then send the random read end command 0xE0, and then the internal data address pointer will move to the position you specified, and the data you will read next is from The data that begins with the specified address.
And the Nand Flash data manual also said that you can operate this random read multiple times without limitation.
Please note that the addresses you passed in above are all column addresses, that is, in-page addresses. That is to say, for Nand Flash with a page size of 2K, the passed-in address should be less than 2048+64= 2112.
However, in actual use of Nand Flash, it seems that this kind of usage is rare. Most of them read data sequentially.
1.3. Software
If you want to write the Nand Flash driver under Linux, you must first figure out the entire framework of this part under Linux. Understand how the system manages your Nand Flash, and the system does the preparations for you, and the rest is to drive the low-level implementation part and what functions you need to implement in order to make the hardware work properly.
1.3.1. Nand Flash related specifications-ONFI and LBA
Before introducing the software details of Nand Flash, let me introduce two related specifications of Nand Flash: ONFI and LBA.
ONFI specification, namely Open Nand Flash Interface specification.
ONFI is led by Intel, and some other manufacturers (Hynix, Micron, Numonyx, Phison, SanDisk, Sony, Spansion, etc.) have participated in the formulation and unified the operating interface of Nand Flash.
The so-called operation interface refers to the content such as commands for operating Nand Flash.
The so-called unification means that the previous Nand Flash operation commands, etc., are all in their own right. Although most common Nand Flash operations, such as page read commands are 0x00, 0x30, page write commands are 0x80, 0x10, etc., but Some command-related content, a very special and very important example is the read id command of each manufacturer’s Nand Flash, although all are 0x90, but the meaning of the few bytes read is defined by each manufacturer They are all different.
Therefore, it is said that the operation interface of Nand Flash is unified.
ONFI specification, the official website can be downloaded to:
http://onfi.org/specifications/
such as:
ONFI 2.2 Spec
http://onfi.org/wp-content/uploads/2009/02/ONFI%202_2%20Gold.pdf
The command set of Nand Flash defined in the ONFI specification is:
Figure 1.13. Nand Flash command set in ONFI
As you can see, some of the common commands, such as
- page read（0x00,0x30）
- page write（0x80,0x10）
- block erase（0x60,0xD0）
- Reset（0xFF）
The commands, etc., are the same as the normal Nand Flash commands, and some additional commands, such as Read Unique ID (0xED), are not available in some previous Nand Flash commands.
In this way, the set of commands for the operation of Nand Flash and the timing followed for sending the corresponding commands are defined.
1.3.1.1.1. ONFI Block Abstracted NAND
ONFI also defines another specification:
ONFI Block Abstracted Nand Specification
http://onfi.org/wp-content/uploads/2009/02/BA_NAND_rev_1_1_Gold.pdf
Namely ONFI LBA Nand, in short, the Nand of logical block addressing. Its meaning is basically the same as Toshiba's LBA.
After the ONFI specification is defined, each manufacturer’s Nand Flash, as long as it conforms to this ONFI specification, and then the upper-level Nand Flash software can be unified and only one type. In other words, after I wrote a Nand Flash driver, You can operate all the Nand Flash compatible with ONFI. The compatibility of the entire Nand Flash, the compatibility of the upper software, and the interoperability are greatly improved.
Moreover, in the same way, since any specification is defined, compatibility and scalability will be taken into account, and ONFI is no exception. For the software that conforms to ONFI specifications, in addition to operating multiple Nand Flash compatible with ONFI, as for the new technology and new process Nand Flash that will appear in the future, as long as it conforms to ONFI specifications, it can also support it. You can work under the old software without changing the upper software and drivers due to the update of Nand Flash. This advantage is good news for the relevant developers who integrate the Nand Flash chip into their own system.
1.3.1.2. What is the LBA specification
LBA Nand Flash, Logical Block Address, logical block addressing Nand Flash, is one of the major Nand Flash manufacturers, Toshiba, independently designed a new generation of Nand Flash specifications.
The reason why it is called logical block addressing is relative to the common addressing of physical blocks of Nand Flash. Common Nand Flash, if you want to read and write data, the corresponding address used is corresponding: block address + page address in block + offset in page = absolute physical address,
This physical block addressing, relatively speaking, has a disadvantage, that is, because the previously mentioned Nand Flash will have bad blocks during use, so when encountering such bad blocks, the bad block management must first destroy them. Block mark, and then copy the data of the bad block to another good block, and then continue to access the new block.
And in the process of reading and writing data, there must be corresponding ECC verification. In many cases, software is used to achieve this part of the work. Even for hardware ECC verification, a small amount of software must be written to manipulate the corresponding registers. , Read the results of ECC verification, of course, don’t forget, there are also corresponding load balancing and other tasks.
This kind of bad block management work is very heavy for software, and the whole system is not easy to implement. Therefore, it gave birth to an idea whether it is possible to check ECC, load balance, and manage bad blocks. , All are put on the hardware implementation, and for the software, I don’t care, I only care about how many blocks are available to me for data reading and writing.
In response to this demand, Toshiba introduced the LBA logic block addressing Nand Flash. In addition to the Nand Flash memory chip, a corresponding hardware control power Controller is added to realize the above-mentioned bad block management, ECC verification, load balancing and other tasks. , So that people who want to use your LBA Nand Flash to develop the corresponding software to drive the LBA Nand Flash work, relatively less things to do, relatively speaking, it reduces the work of software system integration. , Improve the development efficiency, shorten the product listing cycle.
LBA Nand first released the corresponding sample in August 2006.
Find a brief introduction of LBA Nand Flash online:
http://www.toshiba-components.com/prpdf/5678E.pdf
It has already been mass-produced, and even in the previous development process, I used one of its LBA Nand Flash.
Currently, there is no free LBA specification on the Internet. Unless you are engaged in development, you can get the corresponding specification after signing an NDA agreement with Toshiba.
Regarding the Toshiba LBA Nand specification, let me say a little more here (refer to the appendix: lba-core.c):
LBA Nand is divided into three partitions: PNP, VFP and MDP:
- PNP is mainly used to store boot code such as Uboot
- VFP is mainly used to store kernel code such as uImage
- MDP is mainly used to store user data, as well as rootfs and other content
1.3.1.3. Why are there ONFI and LBA
Before explaining why there are ONFI and LBA, let’s give a background introduction:
Currently, Nand Flash manufacturers include Samsung, Toshiba, Intel, Hynix, Micron, Numonyx, Phison, SanDisk, Sony, Spansion, etc.
1.3.1.3.1. Technical explanation
The emergence of ONFI, as explained above, is to unify the interface of Nand Flash and make the software compatibility better;
The emergence of LBA is to ease the various management tasks of Nand Flash in software. The above explanations are actually only technical explanations.
1.3.1.3.2. Realistic interpretation
The reality is that ONFI is dominated by Intel, and some other Nand Flash manufacturers have participated in the development of a set of Nand Flash specifications, but they have not been recognized by the two major Nand Flash manufacturers. One is the first manufacturer to be Samsung. The other is Toshiba, the leader of Nand Flash technology. Therefore, it can be regarded as in the field of Nand Flash, the third child took a bunch of small ones and set a standard, but the boss and second child did not buy it. Therefore, Toshiba, the technical boss of Nand, joined forces with the boss of production to launch another set of standardized LBAs.
This can be called a typical norm dispute.
1.3.1.4. The difference and connection between ONFI and LBA
In general, ONFI is relatively similar in compatibility with the old Nand Flash.
1.3.1.4.1. The difference between ONFI and LBA
In general:
The ONFI specification pays more attention to the definition of the operation interface of the Nand Flash + the definition of the ONFI LBA Nand, and the Toshiba LBA specification focuses on the definition of the Nand of the LBA.
1.3.1.4.2. Connection between ONFI and LBA
ONFI Block Abstracted NAND Specification is basically the same as Toshiba's LBA, except that Toshiba's LBA specification has more other modes and application categories.
In general, it can be divided as follows:
ONFI = Unification of Nand Flash operating interface + ONFI's LBA Nand
Toshiba LBA = equivalent to ONFI's LBA Nand + multiple modes and corresponding different applications
1.3.2. Memory Technology Device, MTD (Memory Technology Device)
MTD is a subsystem of Linux storage devices. The purpose of designing this system is to provide an abstraction layer and an interface for memory devices, so that hardware driver designers can care less about storage formats, such as FTL, FFS2, etc., but only need to It is enough to provide the simplest read/write/erase function of the underlying hardware device. As for how the data is represented to the upper user, the hardware driver designer does not need to care, but the MTD storage device subsystem will do it for you.
The simple explanation for the benefits of the MTD subsystem is that it has helped you implement many functions that you drive designers to implement for previous or other systems. In other words, with MTD, you have to design a Nand Flash driver, and you have to do a lot less, because most of the work is done by MTD for you.
Of course, a "side effect" of this benefit is that it makes it more complicated for people we don't know to understand the entire Linux driver architecture, as well as MTD. However, in general, I feel that the advantages far outweigh the disadvantages. Otherwise, you will not only need to understand, but also do more work and achieve more functions.
In addition, there is another important reason, that is, the particularity of the aforementioned Nand Flash and ordinary hard disk devices:
Limited use of output multiplexing to achieve input and output commands and address/data and other IO interfaces, the smallest unit is a page instead of a common bit, it needs to be erased before writing, etc., which leads to such devices, which cannot treat the hard disk as usual. To operate in the same way, only some special methods can be adopted, which gives birth to a unified abstraction layer for MTD devices.
MTD, Nand Flash, nor flash, and other types of flash devices are unified and abstracted into MTD devices for management. According to the characteristics of these devices, the upper layer implements common operation function encapsulation, and the specific internal implementation of the bottom layer needs to drive the designer Realize it yourself. The specific read/write/erase function of the internal hardware device is what you must implement.
Table 1.4. The difference between MTD devices and hard disk devices
| HARD drives | MTD device |
|---|---|
| Consecutive sectors | Contiguous erasable block |
| The sectors are very small (512B, 1024B) | The erasable block is relatively large (32KB, 128KB) |
| Mainly through two operations to maintain operations: read sector, write sector | Mainly through three operations to maintain operations: read from the erase block, write the erase block, erase and write the erasable block |
| The bad is remapped and hidden by the hardware (at least in the common LBA hard disk devices nowadays) | The bad erasable blocks are not hidden, the software should deal with the corresponding bad block problem |
| The HDD sector does not have the problem of exceeding the erasing life | The erasable block is limited to the number of erasing times, about 104-105 times |
One more sentence, for more information about MTD, if you are interested, go to the MTD homepage in the appendix to see.
Regarding the mtd device driver, if you are interested, you can refer to the article on the MTD device in the appendix. This article introduces the entire MTD framework and process in more detail, so that everyone can understand the entire mtd framework and Nand Flash driver.
1.3.2.1. The code for detecting the ID part of different types of Nand Flash in Linux MTD
Regarding nand flash, because the definition of the content read by the read id of each manufacturer is different, different analysis methods are used for the read id. The following code is written by me before, and I originally planned to do it myself I wrote to recommend the Linux MTD kernel source code, but later I gave up because I didn't understand the specific application process. However, later, I saw that the MTD part of Linux was updated, and a similar approach was added.
This is just for the record, and it can be considered as a reference for those who are interested.
file:\linux-2.6.28.4\drivers\mtd\nand\nand_base.c
/*
* Get the flash and manufacturer id and lookup if the type is supported
*/
static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
struct nand_chip *chip,
int busw, int *maf_id)
{
... ...
chip->chipsize = (uint64_t)type->chipsize << 20;
/* 针对不同的MLC和SLC的nand flash，添加了不同的解析其ID的方法 */
/* Newer devices have all the information in additional id bytes */
if (!type->pagesize) {
int erase_bits, page_base, block_base, old_50nm, new_40nm;
uint8_t id3rd, id4th, id5th, id6th, id7th;
/* The 3rd id byte holds MLC / multichip data */
chip->cellinfo = id3rd = chip->read_byte(mtd);
/* The 4th id byte is the important one */
id4th = chip->read_byte(mtd);
id5th = chip->read_byte(mtd);
id6th = chip->read_byte(mtd);
id7th = chip->read_byte(mtd);
/* printk(KERN_INFO " (ID:%02x %02x %02x %02x %02x %02x %02x) ",
id1st, id2nd, id3rd, id4th, id5th, id6th, id7th); */
if (nand_is_mlc(chip->cellinfo)) {
/*
* MLC:
* 50nm has 5 bytes ID, further read ID will periodically output
* 40nm has 6 bytes ID
*/
/*
* the 4th byte is not the same meaning for different manufature
*/
if (NAND_MFR_SAMSUNG == *maf_id) {
/* samsung MLC chip has several type ID meanings:
(1)50nm serials, such as K9GAG08U0M
(2)40nm serials, such as K9LBG08UXD
*/
/* old 50nm chip will periodically output if read further ID */
old_50nm = (id1st == id6th) && (id2nd == id7th);
/* is 40nm or newer */
new_40nm = id6th & 0x07;
if ((!old_50nm) && new_40nm) {
/*
* Samsang
* follow algorithm accordding to datasheets of:
* K9LBG08UXD_1.3 (40nm),
* ID(hex): EC D7 D5 29 38 41
* this algorithm is suitable for new chip than 50nm
* such as K9GAG08u0D,
* ID(hex): EC D5 94 29 B4 41
*/
int bit236;
/* Calc pagesize, bit0,bit1: page size */
page_base = (1 << 11); /* 2KB */
mtd->writesize = page_base * (1 << (id4th & BIT01));
block_base = (1 << 17); /* 128 KB */
/* Calc block size, bit4,bit5,bit7: block size */
erase_bits = (id4th >> 4) & BIT01; /* get bit4,bit5 */
erase_bits |= (id4th >> 5) & BIT(2); /* get bit7 and combine them */
mtd->erasesize = block_base * (1 << erase_bits);
/* Calc oobsize, bit2,bit3,bit6: oob size */
bit236 = (id4th >> 2) & BIT01; /* get bit2,bit3 */
bit236 |= (id4th >> 4) & BIT(2); /* get bit6 and combine them */
switch (bit236) {
case 0x01:
mtd->oobsize = 128;
break;
case 0x02:
mtd->oobsize = 218;
break;
default:
/* others reserved */
break;
}
}
else {
/*
* Samsang
* follow algorithm accordding to datasheets of:
* K9GAG08U0M (50nm)
* this algorithm is suitable for old 50nm chip
*/
goto slc_algorithm;
}
}
else if (NAND_MFR_TOSHIBA == *maf_id) {
/*
* Toshiba
* follow algorithm guess from ID of TC58NVG3D1DTG00:
* Toshiba MLC TC58NVG3D1DTG00 1GB 8bit 1chip
* 4K+218 512K+27K 3.3V, (ID:98 D3 94 BA 64 13 42)
*/
int bit23;
/* Calc pagesize, bit0,bit1: page size */
page_base = (1 << 10); /* 1KB */
mtd->writesize = page_base * (1 << (id4th & BIT01));
block_base = (1 << 16); /* 64 KB */
/* Calc block size, bit4,bit5: block size */
erase_bits = (id4th >> 4) & BIT01; /* get bit4,bit5 */
mtd->erasesize = block_base * (1 << erase_bits);
/* Calc oobsize, use spare/redundant area bit */
bit23 = (id4th >> 2) & BIT01; /* get bit2,bit3 */
switch (bit23) {
case 0x01:
mtd->oobsize = 128;
break;
case 0x02:
mtd->oobsize = 218;
break;
default:
/* others reserved */
break;
}
/* Get buswidth information: x8 or x16 */
busw = ((id4th >> 6) & BIT(0)) ? NAND_BUSWIDTH_16 : 0;
}
else if (NAND_MFR_MICRON == *maf_id) {
/*
* Micron
* follow algorithm accordding to datasheets of:
* 29F32G08CBAAA
*/
int spare_area_size_bit;
/* Calc pagesize, bit0,bit1: page size */
page_base = (1 << 10); /* 1KB */
mtd->writesize = page_base * (1 << (id4th & 0x03));
block_base = (1 << 16); /* 64 KB */
/* Calc block size, bit4,bit5: block size */
erase_bits = (id4th >> 4) & BIT01; /* get bit4,bit5 */
mtd->erasesize = block_base * (1 << erase_bits);
/* Calc oobsize, use spare/redundant area bit */
spare_area_size_bit = (id4th >> 2) & BIT(0);
if (spare_area_size_bit) /* special oob */
mtd->oobsize = 218;
else /* normal */
mtd->oobsize = mtd->writesize / NAND_PAGE_OOB_RATIO;
/* Get buswidth information: x8 or x16 */
busw = ((id4th >> 6) & BIT(0)) ? NAND_BUSWIDTH_16 : 0;
}
else {
/*
* Others
* FIXME: update follow algrithm,
* according to different manufacture's chip's datasheet
*/
goto slc_algorithm;
}
}
else {
/*
* SLC, only has 4 bytes ID, further read will output periodically, such as:
* Hynix : HY27UG084G2M, only has 4 byte ID,
* following read ID is periodically same as the 1st ~ 4th byte,
* for HY27UG084G2M is : 0xAD 0xDC 0x80 0x15 0xAD 0xDC 0x80 0x15 .....
*/
slc_algorithm:
/* Calc pagesize, bit0,bit1: page size */
page_base = (1 << 10); /* 1KB */
mtd->writesize = page_base * (1 << (id4th & BIT01));
block_base = (1 << 16); /* 64 KB */
/* Calc block size, bit4,bit5: block size */
erase_bits = (id4th >> 4) & BIT01; /* get bit4,bit5 */
mtd->erasesize = block_base * (1 << erase_bits);
/* Calc oobsize, use fixed ratio */
mtd->oobsize = mtd->writesize / NAND_PAGE_OOB_RATIO;
/* Get buswidth information: x8 or x16 */
busw = ((id4th >> 6) & BIT(0)) ? NAND_BUSWIDTH_16 : 0;
}
} else {
/*
* Old devices have chip data hardcoded in the device id table
*/
mtd->erasesize = type->erasesize;
mtd->writesize = type->pagesize;
mtd->oobsize = mtd->writesize / NAND_PAGE_OOB_RATIO;
busw = type->options & NAND_BUSWIDTH_16;
}
/*
* 以上内容，主要是更加不同厂家的nand flash的datasheet，一点点总结出来的算法。
* 最新的Linux的MTD部分，已经添加了类似如上部分的代码。此处贴出来，仅供参考。
*/
/*
* Check, if buswidth is correct. Hardware drivers should set
* chip correct !
*/
if (busw != (chip->options & NAND_BUSWIDTH_16)) {
printk(KERN_INFO "NAND device: Manufacturer ID:"
" 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
(chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
busw ? 16 : 8);
return ERR_PTR(-EINVAL);
}
... ...
}