1.2.15.1. Precautions for Page Program
The writing operation of Nand flash is called Program, which is generally in page units.
Some Nand Flash, such as K9K8G08U0A, support partial page programming (Partial Page Program), but there are some restrictions: in the same page, continuous partial page programming cannot exceed 4 times.
Generally, programming operations are performed in units of pages, and partial page programming is rarely used.
Regarding this part of page programming, it was originally a page write operation, but two or more commands were used to implement it. It seems that the operation is redundant and inefficient, but in fact, there are special considerations:
At least for block erase, the first command 0x60 is the erase setup comman, then the block address to be erased is passed in, and then the erase confirm command 0xD0 is passed in to start Erase operation.
This design of sending commands in two steps to complete a single operation, that is, the command mode of setting first, and then confirming the last, is to avoid unintentional/unanticipated external noises, such as certain noises. A 0x60 command is generated. At this time, even if it is mistakenly regarded as an erase operation by Nand Flash, but there is no subsequent confirmation operation 0xD0, Nand Flash will not erase the data, which makes the data safer and will not be misoperation due to noise .
1.2.15.2. Detailed explanation of the read operation process
Let's take the simplest read operation as an example to explain how to understand the sequence diagram and convert the requirements in the sequence diagram into code.
Before explaining the timing diagram, let us first figure out what we have to do:
From a certain page of Nand Flash, read the data we want.
To implement this function, several parts of knowledge are involved. Even if we don’t know the details of Nand Flash, but through the introduction of the basic knowledge, it is easy to think of at least what commands need to be used based on our common sense. , How to send these commands, how to calculate the required address, how to read the data we want and so on.
Here is a step-by-step explanation, what needs to be done, and how to do it:
1.2.15.2.1. What kind of commands need to be used
First of all, it is necessary to understand what command is used to read data:
According to the previous introduction of the command set of Nand Flash, we know that to read data, the Read command is used. This command requires 2 cycles. The first cycle sends 0x00, and the second cycle sends 0x30.
1.2.15.2.2. Preparatory work before sending the command and the specific meaning of each signal in the timing diagram
After knowing what commands to use, learn how to send these commands.
| prompt | |
|---|---|
| Before starting the explanation, I need to be verbose about the word "enable", in case some readers are the same as me before, when listening to this kind of words, it is the first contact, or if they don't have much contact, they are easy to get confused. Confused (although this vocabulary is the most basic vocabulary for some professionals, 囧). Enable (Enable) refers to the meaning of making (a certain signal) effective and making it effective, and how to "make it" and "enable" it. . . . For example, the CLE line number in the above figure is effective at high level. If it is set to high level at this time, we call it, enabling CLE, which means to make it effective. |
Figure 1.7. Timing diagram of Nand Flash data read operation
| note | |
|---|---|
| This picture comes from Samsung's Nand Flash data sheet (datasheet) of model K9K8G08U0A. |
Let's take a look at the yellow vertical line on the side ① specially marked by me in Figure 6.
The moment of the yellow vertical line is the moment before the command 0x00 of the first cycle of the read operation is sent.
Let us see, at that moment, what value corresponds to the several rows it passes through, and to further understand why we need that value.
- The first line that the yellow vertical line crosses is CLE. Remember the pin of enable (CLE) in the previous introduction, right? CLE, set CLE to 1, it means that what you are going to send into Nand Flash through the I/O multiplex port is a command, not an address or other types of data. Only by setting CLE to 1 and making it effective, can the internal hardware logic be notified. What you will receive next is the command, and the internal hardware logic will put the received command in the command register to realize the correctness later. Otherwise, if you don’t set CLE to 1 to make it valid, the hardware will be at a loss and don’t know if you are passing in data or commands.
- And the second line is CE#, and the value at that moment is 0. The reason is very simple. Since you want to send a command to Nand Flash, you must select it first. Therefore, you must ensure that CE# is low to make it valid, that is, the chip selection is valid.
- The third line is WE#, which means write enable. Because the next step is to write commands to Nand Flash, to make WE# valid, set it to low level.
- In the fourth line, ALE is low level, and ALE is high level active, which means to make it invalid. Correspondingly, the previous introduction makes CLE effective, because the data to be data is the command (the 0x30 of the second cycle of the read command shown in the figure is sent at this time), not the address. If in some other occasions, such as the next time you want to enter the address, you must make it valid, and make CLE invalid.
- The fifth line, RE#, is high at this time and invalid. It can be seen that it is valid only when it becomes low level after the next 6 stages, because at that time, a read command is required to read the data.
- The sixth line is the focus of our introduction. The multiplexed input and output I/O ports. At this moment, there is no input data. Next, in different stages, different data/addresses will be input or output.
- The seventh line, R/B#, high level, indicates R (Ready)/ready, because in the fifth stage, the hardware internal, in the fourth stage, after receiving the read command from the outside, the data of the page A little bit is sent to the page register. During this time, the system is busy working, which belongs to the busy stage. Therefore, R/B# becomes low, indicating that the Busy state is busy.
After introducing the value of each signal at time ① and why it is this value, I believe that at each subsequent time, each value of the corresponding different signal will be analyzed slowly by yourself, and it will be easy to understand the specific operation sequence and The principle is up.
1.2.15.2.3. How to calculate the row address and column address we want to pass in
Before introducing the detailed process of reading data, there is one more thing to do, that is, we must first understand the addresses we want to visit, and how to resolve these addresses, and then pass them in a little bit so that the hardware can recognize them. Row.
Here again take K9K8G08U0A as an example. This Nand Flash has a total of 8192 blocks, each block has 64 pages, and each page is 2K+64 Bytes.
Suppose, we want to access the address of 1208 bytes in the 64th page in the 7000th block. At this time, we must first calculate the specific address:
Physical address
= Block size × block number + page size × page number + page address
=128K×7000 ＋ 2K×64 ＋ 1208
=0x36B204B8
Next, we will take a look at how to convert this actual physical address into the format required by Nand Flash.
Before explaining the composition of the address, let's take a look at the introduction of the address cycle in its datasheet:
Figure 1.8. Nand Flash address cycle composition
Combining the stages 2 and 3 in Figure 1.7 "Timing Diagram of Nand Flash Data Reading Operation" , we can see that there are 5 Nand Flash address cycles, 2 Column cycles and 3 Row cycles. .
- Correspondingly, the column address A0~A10 is the address within the page, and the address range is from 0 to 2047.
Attentive readers may have noticed, why is there an extra A11 here?
In this way, from A0 to A11, there are 12 bits in total, and the range that can be represented is 0~212, that is, 0~4096.
In fact, because we visit the address in the page, we may visit the position of oob, that is, within the 64 bytes range of 2048-2111. Therefore, only 2048~2111 are actually used here to indicate the in-page address. The size of the oob area is 64 bytes.
- Correspondingly, A12～A30 are called page numbers. The page number can be located to which page.
A18～A30 indicate the corresponding block number, that is, which block it belongs to.
After a brief explanation of the address composition, it is easy to analyze the address in the above example.
Note that the following method is wrong:
0x36B204B8 = 11 0110 1011 0010 0000 0 100 1011 1000, respectively allocated to 5 address cycles is:
| 1st cycle | A7 ～ A0 | 1011 1000 = 0xB8 |
| 2nd cycle | A11～ A8 | 0100 = 0x04 |
| 3rd period | A19～A12 | 0010 0000 = 0x20 |
| 4th cycle | A27 ～ A20 | 0110 1011 = 0x6B |
| 5th cycle | A30 ～ A28 | 11 = 0x03 |
| note | |
|---|---|
| Corresponding to Figure 1.7 "Timing Diagram of Nand Flash Data Reading Operation" , *L means ground level. Since those bits are not used, it is mandatory to set to 0 in the datasheet, so there is the 2nd cycle above. The upper 4 bits in the middle are 0000. The other bits after A30 are similar in principle, all are 0. |
As for why the above calculation method is wrong, it is because in the above calculation process, the value of the 11th bit, which originally belongs to the bit A11 of the page number, is calculated as the value in the address in the page.
It should be calculated like this, which is correct:
0x36B204B8 = 11 0110 1011 0010 0000 0100 1011 1000
| 1st cycle | A7 ～ A0 | 1011 1000 = 0xB8 |
| 2nd cycle | A10 ～ A8 | 100 = 0x04 |
| 3rd period | A19～A12 | 010 0000 0 = 0x40 |
| 4th cycle | A27 ～ A20 | 110 1011 0 = 0xD6 |
| 5th cycle | A30 ～ A28 | 11 0 = 0x06 |
Someone may ask. In Table 11 above, it is not the clearly written A0 to A30, which includes A11. Doesn't it correspond to the bit0 to bit30 in the address here?
In fact, I made the same mistake at the beginning. I mistakenly thought that each bit of the address we were going to pass in corresponds to A0 to A30 in Table 11. In fact, A11 in Table 11 is quite special. Only when the address in the page we visit is in the position of oob, that is, it belongs to 2048~2111, A11 will be effective, and A0-A11 will be used to indicate a corresponding value from 2048 to 2111, which belongs to oob Somewhere.
And our in-page address here is 2108, which has not exceeded 2047, so A11 must be 0.
This explanation is very convoluted and difficult to understand.
To explain it in another way, it will be easier to understand:
To put it bluntly, we just want to visit the 1208 byte on the 64th page in the 7000th block, which corresponds to
In-page address
=1208
=0x4B8
Page number
= Number of blocks × number of pages / block + page number in the block
= 7000×（128K/2K） + 64
= 7000×64 + 64
= 448064
=0x6D640
That is, we want to access the address 0x4B8 in page 0x6D640, so it's easy to understand, ^_^.
Then the corresponding:
In-page address=0x4B8
Divided into two corresponding column addresses, it becomes
0x4B8: column address 1=0xB8, column address 2=0x04
Page number=0x6D640, divided into three line numbers:
0x6D640: line number 1=0x40, line number 2=0xD6, line number 3=0x06
Looking back at the calculation method above,
Calculated at the beginning:
Column address 1=0xB8
Column address 2=0x04
Line number 1=0x20
Line number 2=0x6B
Line number 3=0x03
it's wrong.
And the second calculation is correct:
Column address 1=0xB8
Column address 2=0x04
Line number 1=0x40
Line number 2=0xD6
Line number 3=0x06
That's right, and it's consistent with our own manual calculation here.
The first time the calculation was wrong was that the lowest bit A11 of the row address was mistakenly placed in the highest bit of the column address.
At this point, it is considered how to manually calculate the row address and column address, and the explanation is clear and correct.
Correspondingly, in the Linux source code \drivers\mtd\nand\nand_base.c, this is also handled:
static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
int column, int page_addr)
{
......
/* Serially input address */
if (column != -1) {
......
chip->cmd_ctrl(mtd, column, ctrl); /* 发送Col Addr 1 */
ctrl &= ~NAND_CTRL_CHANGE;
chip->cmd_ctrl(mtd, column >> 8, ctrl); /* 发送Col Addr 2 */
}
if (page_addr != -1) {
chip->cmd_ctrl(mtd, page_addr, ctrl); /* 发送Row Addr 1 */
chip->cmd_ctrl(mtd, page_addr >> 8, /* 发送Row Addr 2 */
NAND_NCE | NAND_ALE);
/* One more address cycle for devices > 128MiB */
if (chip->chipsize > (128 << 20))
chip->cmd_ctrl(mtd, page_addr >> 16, /* 发送Row Addr 3 */
NAND_NCE | NAND_ALE);
}
}
| Column, that is, the address in the page, in most cases, it is 0, even if it is not 0, you can directly divide the incoming address by the page address and the remainder is the column address. |
|
| page_addr is the page number, and it is also very simple. It can be obtained by dividing the address to be accessed by the page size. |
Therefore, if we want to access the 1208 bytes in the 64th page in the 7000th block, the address to be passed in is divided into 5 cycles:
Pass in two column addresses respectively:
Column address 1=0xB8
Column address 2=0x04
Then pass 3 line addresses:
Line number 1=0x40
Line number 2=0xD6
Line number 3=0x06
So that the hardware can be recognized.
The next content is to introduce how the hardware handles these inputs.
1.2.15.2.4. Interpretation of the read operation process
The preparatory work is finally over, and the following can begin to explain, for the read operation, the 1-6 stages marked in the figure above, what are the specific meanings.
Operation preparation stage: This is the Read operation, so first send a 0x00 in the first stage of the read command in Figure 5, which means that the hardware should be prepared first, and the next operation is reading.
Send the column address for two cycles. That is, the address in the page, which indicates where I want to start reading data on a page.
Next, pass in three more row addresses. The corresponding is the page number.
Then send the command 0x30 of the second cycle of a read operation. Next, it's the hardware's own business.
Nand Flash's internal hardware logic is responsible for finding which page in which block according to your requirements and according to the incoming address, and then moving the entire page of data to the page cache bit by bit. In the meantime, all you can do is to read the status register to see the value of the corresponding bit, that is, the bit of R/B#, if it is 1 or 0, it means, The system is busy and is still "busy" (reading data). If it is 1, it means that the system is finished, and it is busy. The data of the entire page has been moved to the page cache. You can proceed Read the data you want.
For here. It is estimated that someone will ask, this page is 2048+64 bytes in total. If I pass in the page address, like the value of 1208 given above, I just want to read the data from 1028 to 2011 instead of the page. Isn’t it wasteful that the internal hardware reads the data of the entire page at address 0 at the beginning? The answer is that it is really wasteful and the efficiency does not seem to be high, but it is actually done, and it takes a relatively short time to read the data of the entire page, and after reading it out, the internal data pointer will be positioned to the one you just made The position of 1208.
Next, it's time for you to "steal" the results of your labor after the system has been busy for a long time, ha ha. By first going to the data register of the Nand Flash controller to write how many bytes/words you want to read, then you can go to the FIFO of the Nand Flash controller and read you a little bit The data is needed.
At this point, the entire Nand Flash read operation is completed.
For other operations, you can read the datasheet a little bit by yourself according to my analysis above, analyze the specific operation process according to the sequence diagram inside, and then compare the code, it will be more clear how to implement it.