The previous tweet has covered the three major aspects of the STM32 network
①PHY interface, " STM32 network circuit design "
②MAC controller, " MAC controller for STM32 network "
③DMA controller, " DMA controller for STM32 network "
This article will focus on the interruption system of the STM32 network, and briefly talk about the interruption system and its usage.
01. Introduction
Network interrupt vector: one is used for normal network operations, and the other is used for Ethernet wake-up events when it is mapped to EXIT line 19 (with wake-up frame or magic packet detection)
The first network interrupt is reserved for the interrupt generated by the MAC and DMA, as in the MAC interrupt and DMA interrupt section.
The second interrupt is reserved as the interrupt generated by the PMT during the wake-up event. The mapping of the wake-up event to the EXIT line 19 causes the STM32F20X and STM32F21X to exit the low-power mode and generate an interrupt.
When the Ethernet wake-up event mapped to the EXIT line 19 occurs and the MACPMT interrupt is enabled and the EXIT line 19 interrupt with a rising edge is also enabled, they can all wake up the interrupt.
The watchdog timer (see ETH_DMARSWTR register) can be used to flexibly control the RS bit (ETH_DMASR register). When the watchdog timer is programmed with a non-zero value, the watchdog timer is activated, as long as RXDMA finishes sending a received data frame to the system storage, in the state of not triggering the reception, because it is not enabled in the corresponding reception Descriptor (RDES1[31]) (that is: the receiving state is not enabled in the corresponding receive descriptor (RDES1[31])). When the timer runs according to the programmed value, the RS bit is set to 1 and an interrupt occurs, if the corresponding bit in the ETH_DMAIER register is enabled. The watchdog timer expires before running, when the data frame is sent to the memory, and RS is set to 1, because the timer is enabled as a descriptor.
note:
Reading the PMT control and status register will automatically clear the PMT interrupt flag of the received wake-up frame and the received magic packet. However, since the registers used for these flags are located in the CLK_RX domain, there may be a significant delay before the firmware can detect this update. This delay can be particularly long when the RX clock is very slow (in 10 Mbit mode) and when the AHB bus is high-frequency.
Since the interrupt request from the PMT to the CPU is based on the same register in the CLK_RX domain, even after reading the PMT_CSR, the CPU may call the interrupt routine a second time by mistake. Therefore, it may be necessary for the firmware to poll the received wake-up frame and the received magic packet bit, and exit the interrupt service routine only when it finds that they are both '0'.
02, code
The network interrupt of STM32 is actually the interrupt of the network-specific DMA. The data packet in the network conforms to the 1518 rule, that is to say, it is 1460 bytes. The data packet received by the MAC is 2K bytes. Every data on the network After receiving the packet MAC, an interrupt will be generated.
The official code is like this
Obviously, the query method is used, and the interrupt is not used.
The interrupts are used as follows:
Configure network outage
Comment out the code in the query part provided by the official.
After we use the interrupt form, the code is
With such a code, we have no problem receiving data smaller than the data size of a DMA descriptor, and it is very smooth.
Please see " DMA Controller of STM32 Network " for the content of DMA descriptor .
When receiving a large amount of data, an error will occur, the receiving will be slow, and the receiving too much will crash
The solution is:
Modify if to while
In this way, the interrupt will be jumped out after receiving the entire data packet, which solves the problem.
Click to view the album where this article is located, STM32F207 tutorial
Pay attention to the official account, and receive article updates as soon as possible .
